AD73322LAST-REEL Analog Devices Inc, AD73322LAST-REEL Datasheet - Page 18

• Manufacturer Part Number: AD73322LAST-REEL
• Description: IC ANALOG FRONT END DUAL 44-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD73322LAST-REEL

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 44-LQFP

AD73322L
DIGITAL GAIN TAP
The digital gain tap features a programmable gain block whose
input is taken from the bit stream output of the ADC’s sigma
delta modulator. This single bit input (1 or 0) is used to add or
subtract a programmable value, which is the digital gain tap
setting, to the output of the DAC section’s interpolator. The
programmable setting has 16-bit resolution and is programmed
using the settings in Control Registers G and H, as shown in
Table 11. In this table, AGT and DGT weights are given for the
case of VFBNx (connected to the sigma-delta modulator’s
positive input) being at a higher potential than VFBPx
(connected to the sigma-delta modulator’s negative input).
Table 11. Digital Gain Tap Settings
DGT15–0 (Hex)
0x8000
0x9000
0xA000
0xC000
0xE000
0x0000
0x2000
0x4000
0x6000
0x7FFF
SERIAL PORT (SPORT)
The codecs communicate with a host processor via the
bidirectional synchronous serial port (SPORT), which is
compatible with most modern DSPs. The SPORT is used to
transmit and receive digital data and control information. The
dual codec is implemented using two separate codec blocks that
are internally cascaded with serial port access to the input of
Codec 1 and the output of Codec 2. This allows other single or
dual codec devices to be cascaded together (up to a limit of
eight codec units).
In both transmit and receive modes, data is transferred at the
serial clock (SCLK) rate with the MSB being transferred first.
Due to the fact that the SPORT of each codec block uses a
common serial register for serial input and output, commun-
ications between an AD73322L codec and a host processor
(DSP engine) must always be initiated by the codecs themselves.
In this configuration, the codecs are described as being in
master mode. This ensures that there is no collision between
input data and output samples.
Gain
−1.00
−0.875
−0.75
−0.5
−0.25
0.00
+0.25
+0.05
+0.75
+0.99999
Rev. A | Page 18 of 48
SPORT OVERVIEW
The AD73322L SPORT is a flexible, full-duplex, synchronous
serial port having a protocol designed to allow up to four
AD73322L devices (or combinations of AD73322L dual
codecs and AD73311 single codecs up to eight codec blocks) to
be connected, in cascade, to a single DSP via a 6-wire interface.
It has a very flexible architecture that can be configured by
programming two of the internal control registers in each codec
block. The device has three distinct modes of operation: control
mode, data mode, and mixed control/data mode.
Note that because each codec has its own SPORT section, the
register settings in both SPORTs must be programmed. The
registers that control SPORT and sample rate operation
(CRA and CRB) must be programmed with the same values,
otherwise incorrect operation may occur.
In control mode (CRA:0 = 0), the device’s internal configuration
can be programmed by writing to the eight internal control
registers. In this mode, control information can be written to or
read from the codec. In data mode (CRA:0 = 1), (CRA:1 = 0),
information sent to the device is used to update the decoder
section (DAC), while the encoder section (ADC) data is read
from the device. In this mode, only DAC and ADC data are
written to or read from the device. Mixed mode (CRA:0 = 1
and CRA:1 = 1) allows the user to choose whether the infor-
mation being sent to the device contains control information
or DAC data. This is achieved by using the MSB of the 16-bit
frame as a flag bit. Mixed mode reduces the resolution to 15 bits
with the MSB being used to indicate whether the information in
the 16-bit frame is control information or DAC/ADC data.
The SPORT features a single 16-bit serial register that is used
for both input and output data transfers. As the input and
output data must share the same register, some precautions
must be observed. The primary precaution is that no informa-
tion must be written to the SPORT without reference to an
output sample event, which is when the serial register is
overwritten with the latest ADC sample word. Once the SPORT
starts to output the latest ADC word, it is safe for the DSP to
write new control or data-words to the codec. In certain con-
figurations, data can be written to the device to coincide with
the output sample being shifted out of the serial register — see
the Interfacing section. The serial clock rate (CRB:2–3) defines
how many 16-bit words can be written to a device before the
next output sample event happens.