AD73322LAST-REEL Analog Devices Inc, AD73322LAST-REEL Datasheet
AD73322LAST-REEL
Specifications of AD73322LAST-REEL
Related parts for AD73322LAST-REEL
AD73322LAST-REEL Summary of contents
Page 1
FEATURES Two 16-bit A/D converters Two 16-bit D/A converters Programmable input/output sample rates 78 dB ADC SNR 78 dB DAC SNR 64 kHz maximum sample rate −90 dB crosstalk Low group delay (25 µs typ per ADC channel, 50 µs ...
Page 2
AD73322L TABLE OF CONTENTS Specifications..................................................................................... 4 Current Summary......................................................................... 6 Signal Ranges ................................................................................ 7 Timing Characteristics ................................................................ 7 Timing Diagrams.......................................................................... 8 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configurations and Function Descriptions ......................... 10 Terminology .................................................................................... 12 Abbreviations .............................................................................. 12 ...
Page 3
Analog Output.............................................................................34 Differential-to-Single-Ended Output .......................................35 Digital Interfacing .......................................................................35 Cascade Operation......................................................................35 Grounding and Layout ...............................................................36 DSP Programming Considerations ..............................................37 DSP SPORT Configuration .......................................................37 DSP SPORT Interrupts...............................................................37 DSP Software Considerations When Interfacing to the AD73322L ....................................................................................37 Operating Mode ..........................................................................37 REVISION HISTORY 12/04—Rev. ...
Page 4
AD73322L SPECIFICATIONS AVDD = 3 V ± 10%; DVDD = 3 V ± 10%; DGND = AGND = unless otherwise noted. Operating temperature range as follows: A grade, T Table 1. Parameter REFERENCE REFCAP Absolute Voltage, VREFCAP ...
Page 5
Parameter 3, 4 Group Delay Input Resistance at PGA DIGITAL GAIN TAP Gain at Maximum Setting Gain at Minimum Setting Gain Resolution Delay Settling Time DAC SPECIFICATIONS 1 Maximum Voltage Output Swing Single-Ended Differential Nominal Voltage Output ...
Page 6
AD73322L Parameter 0.0625 0.125 0.1875 0.25 0.3125 0.375 0.4375 > 0.5 LOGIC INPUTS V , Input High Voltage INH V , Input Low Voltage INL I , Input Current Input Capacitance IN LOGIC OUTPUT V , Output ...
Page 7
SIGNAL RANGES Table 3. Mnemoic Description VREFCAP VREFOUT ADC Maximum input range at V Nominal reference level DAC Maximum voltage output swing Single-Ended Differential Nominal voltage output swing Single-Ended Differential Output bias voltage TIMING CHARACTERISTICS AVDD = 3 V ± ...
Page 8
AD73322L TIMING DIAGRAMS SE (I) THREE- STATE SCLK (O) SDIFS (I) SDI ( THREE- STATE SDOFS (O) THREE- STATE SDO ( Figure 2. MCLK Timing 100µ OUTPUT PIN C ...
Page 9
ABSOLUTE MAXIMUM RATINGS T = 25°C unless otherwise noted. A Table 5. Parameters Ratings AVDD, DVDD to GND −0 +4.6 V AGND to DGND −0 +0.3 V Digital I/O Voltage to DGND −0 (DVDD ...
Page 10
AD73322L PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VINP1 1 VFBP1 2 VINN1 3 VFBN1 4 AD73322L REFOUT 5 TOP VIEW REFCAP 6 (Not to Scale) AVDD2 7 AGND2 8 DGND 9 DVDD 10 RESET 11 SCLK 12 MCLK 13 SDO 14 ...
Page 11
Mnemonic Function SCLK Serial Clock Output. This rate determines the serial transfer rate to/from the codec used to clock data or control information to and from the serial port (SPORT). The frequency of SCLK is equal to the ...
Page 12
AD73322L TERMINOLOGY Absolute Gain A measure of converter gain for a known signal. Absolute gain is measured (differentially) with a 1 kHz sine wave at 0 dBm0 for the DAC and with a 1 kHz sine wave at 0 dBm0 ...
Page 13
TYPICAL PERFORMANCE CHARACTERISTICS AND FUNCTIONAL BLOCK DIAGRAM –10 –85 –75 –65 –55 –45 –35 V (dBm0) IN Figure 9. S/N vs. V (ADC @ 3 V) over Voice Bandwidth ...
Page 14
AD73322L FUNCTIONAL DESCRIPTIONS ENCODER CHANNELS Both encoder channels consist of a pair of inverting op amps with feedback connections that can be bypassed if required, a switched capacitor PGA and a sigma-delta analog-to-digital converter (ADC). An on-board digital filter, which ...
Page 15
Figure 15 shows the response of the digital decimation filter (sinc-cubed response) with nulls every multiple of DMCLK/256 corresponding to the decimation filter update rate for a 64 kHz sampling. The nulls of the Sinc3 response correspond with multiples of ...
Page 16
AD73322L In mixed control/data mode, the resolution is fixed at 15 bits, with the MSB of the 16-bit transfer being used as a flag bit to indicate either control or data in the frame. DECODER CHANNEL The decoder channels consist ...
Page 17
MCLK EXTERNAL DMCLK INTERNAL MCLK DIVIDER 3 SE SERIAL PORT 1 (SPORT 1) RESET SDIFS SDI SERIAL REGISTER CONTROL CONTROL CONTROL REGISTER REGISTER REGISTER CONTROL CONTROL REGISTER REGISTER 1G CONTROL REGISTER 1H ...
Page 18
AD73322L DIGITAL GAIN TAP The digital gain tap features a programmable gain block whose input is taken from the bit stream output of the ADC’s sigma delta modulator. This single bit input ( used to add or ...
Page 19
The SPORT block diagram shown in Figure 19 details the blocks associated with Codecs 1 and 2, including the eight control registers (A–H), external MCLK to internal DMCLK divider, and serial clock divider. The divider rates are controlled by the ...
Page 20
AD73322L DAC ADVANCE REGISTER The loading of the DAC is internally synchronized with the unloading of the ADC data in each sampling interval. The default DAC load event happens one SCLK cycle before the SDOFS flag is raised by the ...
Page 21
CONTROL REGISTER A Table 18. Control Register A Description RESET DC2 DC1 Bit Name 0 DATA/PGM DLB 3 SLB 4 DC0 5 DC1 6 DC2 7 RESET CONTROL REGISTER B Table 19. Control Register ...
Page 22
AD73322L CONTROL REGISTER D Table 21. Control Register D Description MUTE OGS2 OGS1 Bit Name Description 0 IGS0 Input Gain Select (Bit 0) 1 IGS1 Input Gain Select (Bit 1) 2 IGS2 Input Gain Select (Bit 2) ...
Page 23
CONTROL REGISTER G Table 24. Control Register G Description DGTC7 DGTC6 DGTC5 Bit Name 0 DGTC0 1 DGTC1 2 DGTC2 3 DGTC3 4 DGTC4 5 DGTC5 6 DGTC6 7 DGTC7 CONTROL REGISTER H Table 25. Control Register ...
Page 24
AD73322L OPERATION RESETTING THE AD73322L The RESET pin resets all the control registers. All registers are reset to zero, indicating that the default SCLK rate (DMCLK/8) and sample rate (DMCLK/2048) are at a minimum to ensure that slow speed DSP ...
Page 25
DATA MODE Once the device has been configured by programming the correct settings to the various control registers, the device may exit program mode and enter data mode. This is done by programming the DATA/ PGM (CRA:0) bit to a ...
Page 26
AD73322L ANALOG LOOP-BACK MODE In analog loop-back mode, the differential DAC output is connected, via a loop-back switch, to the ADC input, as shown in Figure 22. This mode allows the ADC channel to check functionality of the DAC channel ...
Page 27
INTERFACING The AD73322L can be interfaced to most modern DSP engines using conventional serial port connections and an extra enable control line. Both serial input and output data use an accom- panying frame synchronization signal that is active high one ...
Page 28
AD73322L Each bit will take 1/SCLK and, allowing for any latency between the receipt of the Rx interrupt and the transmission of the Tx data, the relationship for successful operation is given by M/DMCLK > ((N × 16/SCLK ...
Page 29
PERFORMANCE Because the AD73322L is designed to provide high perfor- mance and low cost conversion important to understand how high performance can be achieved in a typical application. By means of spectral graphs, this section outlines the typical ...
Page 30
AD73322L In the case of voice-band processing where 4 kHz represents the Nyquist frequency, if the signal to be measured were externally band-limited, then an 8 kHz sampling rate would suffice. However, if the bandwidth must be limited with a ...
Page 31
Because the AD73322L can be operated at 8 kHz (see Figure 31 kHz sampling rates, which make it particularly suited for voice-band processing, the user must understand the action of the interpolator’s sinc3 response. As was the case ...
Page 32
AD73322L DESIGN CONSIDERATIONS The AD73322L features both differential inputs and outputs on each channel to provide optimal performance and avoid common-mode noise also possible to interface either inputs or outputs in single-ended mode. This section details the choice ...
Page 33
The AD73322L’s ADC inputs are biased about the internal reference level (REFCAP level); therefore, it may be necessary to bias external signals to this level using the buffered REFOUT level as the reference. This is applicable in either dc-coupled or ...
Page 34
AD73322L INTERFACING TO AN ELECTRET MICROPHONE Figure 39 details an interface for an electret microphone which may be used in some voice applications. Electret microphones typically feature a FET amplifier whose output is accessed on the same lead which supplies ...
Page 35
DIFFERENTIAL-TO-SINGLE-ENDED OUTPUT In some applications it may be desirable to convert the full differential output of the decoder channel to a single-ended signal. The circuit of Figure 42 shows a scheme for doing this. V REF VINP1 VFBP1 R F ...
Page 36
AD73322L GROUNDING AND LAYOUT Because the analog inputs to the AD73322L are differential, most of the voltages in the analog modulator are common- mode voltages. The excellent common-mode rejection of the part removes common-mode noise on these inputs. The analog ...
Page 37
DSP PROGRAMMING CONSIDERATIONS This section discusses how the serial port of the DSP should be configured and the implications of whether Rx and Tx interrupts should be enabled. DSP SPORT CONFIGURATION Following are the key settings of the DSP SPORT ...
Page 38
AD73322L INITIALIZATION Following reset, the AD73322L is in its default condition, which ensures that the device is in control mode and must be programmed or initialized from the DSP to start conversions. Because communications between AD73322L and the DSP are ...
Page 39
At each occurrence of an SDOFS pulse, the DSP’s transmit buffer contents are sent to the SDI pin of the AD73322L. This also causes a subsequent DSP Tx interrupt which transfers the initialization word, pointed to by the circular buffer ...
Page 40
AD73322L DAC TIMING CONTROL EXAMPLE The AD73322L’s DAC is loaded from the DAC register contents just before the ADC register contents are loaded to the serial register (SDOFS going high). This default DAC load position can be advanced in time ...
Page 41
CONFIGURING AN AD73322L TO OPERATE IN DATA MODE This section describes the typical sequence of control words that are required to be sent to an AD73322L to set it up for data 1 mode operation. In this sequence, Registers B, ...
Page 42
AD73322L Table 27. Data Mode Operation Step DSP Tx 1 Control Word CRB–CH2 -> 1000100100001011 2 Control Word CRB–CH1 -> 1000000100001011 3 At this time, Control Register B of both Channel 1 and Channel 2 are updated. 4 Control Word ...
Page 43
CONFIGURING AN AD73322L TO OPERATE IN MIXED MODE This section describes a typical sequence of control words that would be sent to an AD73322L to configure it for operation in 1 mixed mode not intended ...
Page 44
AD73322L Table 28. Mixed Mode Operation Step DSP CRA-CH2 -> 1000100000010011 4 CRA-CH1 -> 1000000000010011 CRB-CH2 -> 1000100100001011 9 CRB-CH1 -> 1000000100001011 10 The ADC data from both channels has been read ...
Page 45
Step DSP The ADC data of both channels has been read, and a readback of Control Register C has been performed DAC WORD CH 2 -> 0111111111111111 29 DAC WORD CH 1 -> 1000000000000000 ...
Page 46
AD73322L OUTLINE DIMENSIONS 18.10 (0.7126) 17.70 (0.6969 7.60 (0.2992) 7.40 (0.2913 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) 1.27 (0.0500) SEATING 0.51 (0.0201) COPLANARITY BSC PLANE 0.31 (0.0122) 0.10 COMPLIANT TO JEDEC STANDARDS MS-013AE CONTROLLING ...
Page 47
... AD73322LARUZ 1 −40°C to +85°C AD73322LARUZ-REEL −40°C to +85°C 1 AD73322LAST −40°C to +85°C AD73322LAST-REEL −40°C to +85°C AD73322LYR −40°C to +105°C AD73322LYR-REEL −40°C to +105°C AD73322LYR-REEL7 −40°C to +105°C AD73322LYRU −40°C to +105°C AD73322LYRU-REEL − ...
Page 48
AD73322L NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00691–0–12/04(A) Rev Page ...