AD73311LAR-REEL Analog Devices Inc, AD73311LAR-REEL Datasheet - Page 10

• Manufacturer Part Number: AD73311LAR-REEL
• Description: IC ANALOG FRONT END 20-SOIC T/R
• Manufacturer: Analog Devices Inc

Specifications of AD73311LAR-REEL

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 2
• Power (watts): 50mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 20-SOIC (7.5mm Width)

AD73311L
Decimation Filter
The digital filter used in the AD73311L carries out two impor-
tant functions. Firstly, it removes the out-of-band quantization
noise, which is shaped by the analog modulator and secondly, it
decimates the high frequency bitstream to a lower rate 15-bit word.
The antialiasing decimation filter is a sinc-cubed digital filter
that reduces the sampling rate from DMCLK/8 at the modula-
tor to an output rate at the SPORT of DMCLK/M (where M
depends on the sample rate setting—M = 256 @ 64 kHz; M =
512 @ 32 kHz, M = 1024 @ 16 kHz, M = 2048 @ 8 kHz), and
increases the resolution from a single bit to 15 bits. Its Z trans-
form is given as: [(1–Z
the sampling rate (N = 32 @ 64 kHz, N = 64 @ 32 kHz, N =
128 @ 16 kHz, N = 256 @ 8 kHz). This ensures a minimal
group delay of 25 µs at the 64 kHz sampling rate.
F
F
B
F
B
B
= 4kHz
= 4kHz
F
= 4kHz FS
B
= 4kHz FS
SIGNAL TRANSFER FUNCTION
INTER
FINAL
–N
= DMCLK/256
)/(1–Z
= 8kHz FS
NOISE TRANSFER FUNCTION
–1
)]
INTER
3
where N is determined by
= DMCLK/256
FS
FS
INIT
INIT
= DMCLK/8
= DMCLK/8
ADC Coding
The ADC coding scheme is in twos complement format (see
Figure 8). The output words are formed by the decimation
filter, which grows the word length from the single-bit output of
the sigma-delta modulator to a 15-bit word, which is the 16-bit
transfer being used as a flag bit to indicate either control or data
in the frame.
Decoder Channel
The decoder channel consists of a digital interpolator, digital
sigma-delta modulator, a single bit digital-to-analog converter
(DAC), an analog smoothing filter and a programmable gain
amplifier with differential output.
DAC Coding
The DAC coding scheme is in twos complement format with
0x7FFF being full-scale positive and 0x8000 being full-scale
negative.
Interpolation Filter
The anti-imaging interpolation filter is a sinc-cubed digital filter
which up-samples the 16-bit input words from the SPORT
input rate of DMCLK/M (where M depends on the sample rate
setting—M = 256 @ 64 kHz; M = 512 @ 32 kHz, M = 1024 @
16 kHz, M = 2048 @ 8 kHz), to a rate of DMCLK/8 while
filtering to attenuate images produced by the interpolation pro-
cess. Its Z transform is given as: [(1–Z
determined by the sampling rate (N = 32 @ 64 kHz, N = 64 @
32 kHz, N = 128 @ 16 kHz, N = 256 @ 8 kHz). The DAC
receives 16-bit samples from the host DSP processor at a rate of
DMCLK/M. If the host processor fails to write a new value to
the serial port, the existing (previous) data is read again. The
data stream is filtered by the anti-imaging interpolation filter,
but there is an option to bypass the interpolator for the mini-
mum group delay configuration by setting the IBYP bit (CRE:5) of
Control Register E. The interpolation filter has the same charac-
teristics as the ADC’s antialiasing decimation filter.
ANALOG
ANALOG
INPUT
INPUT
V
V
V
REF
REF
V
REF
REF
+ (V
– (V
– (V
+ (V
REF
REF
REF
REF
0.32875)
0.32875)
0.6575)
0.6575)
V
V
REF
REF
10...00
10...00
ADC CODE SINGLE-ENDED
ADC CODE DIFFERENTIAL
V
V
INN
V
V
INN
–N
INP
INP
00...00
00...00
)/(1–Z
–1
)]
3
01...11
01...11
where N is