AD9879BS Analog Devices Inc, AD9879BS Datasheet - Page 6

• Manufacturer Part Number: AD9879BS
• Description: IC FRONT-END MIXED-SGNL 100-MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9879BS

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Number Of Channels: 5
• Power (watts): 587mW
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 100-MQFP, 100-PQFP

AD9879
Parameter
CHANNEL-TO-CHANNEL ISOLATION
TIMING CHARACTERISTICS (10 pF Load)
CMOS LOGIC INPUTS
CMOS LOGIC OUTPUTS (1 mA Load)
POWER SUPPLY
1
IQ ADC in default mode. ADC Clock Select Register 8, Bit 3 set to 0.
Tx DAC-to-ADC Isolation (A
Isolation Between Tx and IQ ADCs
Isolation Between Tx and 10-Bit ADC
Isolation Between Tx and 12-Bit ADC
ADC-to-ADC (A
Isolation Between IF10 and IF12 ADCs
Isolation Between Q and I Inputs
Minimum RESET Pulse Width Low (t
Digital Output Rise/Fall Time
Tx/Rx Interface
MCLK Rising Edge to
REFCLK Rising or Falling Edge to
REFCLK Edge to MCLK Falling Edge (t
Serial Control Bus
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Supply Current, I
Supply Current, I
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
MCLK Frequency (f
TxSYNC/TxIQ Setup Time (t
TxSYNC/TxIQ Hold Time (t
RxSYNC/RxIQ/IF Valid Delay (t
RxSYNC/RxIQ/IF Valid Delay (t
Maximum SCLK Frequency (f
Minimum Clock Pulse Width High (t
Minimum Clock Pulse Width Low (t
Maximum Clock Rise/Fall Time
Minimum Data/Chip-Select Setup Time (t
Minimum Data Hold Time (t
Maximum Data Valid Time (t
Analog Supply Current, I
Digital Supply Current, I
Standby (PWRDN Pin Active)
Full Power-Down (Register 0x02 = 0xF9)
Power-Down Tx Path (Register 0x02 = 0x60)
Power-Down Rx Path (Register 0x02 = 0x19)
IN
S
S
= –0.5 dBFS, f = 5 MHz)
(Full Operation)
MCLK
)
DS
AS
OUT
HD
SU
DH
= 5 MHz)
)
DV
SCLK
)
MD
OD
)
)
)
)
)
RL
)
EE
PWL
PWH
)
)
)
DS
)
Temp
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
N/A
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Rev. A | Page 6 of 32
Test Level
II
II
II
III
III
III
III
III
N/A
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
III
III
II
III
III
III
Min
46.2
44.9
5
2.8
3
3
0
T
−1.0
30
30
25
0
V
V
OSC
DRVDD
DRVDD
/4 – 2.0
– 0.7
– 0.6
Typ
57.2
−50.1
53.4
>60
>80
>80
>85
>50
3
163
95
68
119
16
113
110
Max
−44.5
4
66
1.0
T
+1.0
15
1
30
0.4
12
12
0.4
184
126
OSC
/4 + 3.0
Unit
Bits
dB
dB
dB
dB
dB
dB
dB
t
ns
MHz
ns
ns
ns
ns
ns
MHz
ns
ns
ms
ns
ns
ns
V
V
µA
µA
pF
V
V
mA
mA
mA
mA
mA
mA
mA
MCLK
cycles