AD9879BS Analog Devices Inc, AD9879BS Datasheet
AD9879BS
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AD9879BS Summary of contents
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FEATURES Low cost 3.3 V MxFE™ for DOCSIS-, EURO-DOCSIS-, DVB-, DAVIC-compliant set-top box and cable modem applications 232 MHz quadrature digital upconverter 12-bit direct IF DAC (TxDAC+™ MHz carrier frequency DDS Programmable sampling clock rates 16× upsampling ...
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AD9879 TABLE OF CONTENTS Specifications..................................................................................... 4 Absolute Maximum Ratings............................................................ 7 Explanation of Test Levels ........................................................... 7 Thermal Characteristics .............................................................. 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Terminology .................................................................................... 10 Theory of Operation ...................................................................... 11 Transmit Path.............................................................................. 11 ...
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REVISION HISTORY 6/05—Rev Rev. A Updated Format.................................................................. Universal Changed OSCOUT to REFCLK....................................... Universal Changed REF CLK to REFCLK........................................ Universal Changes to Specifications Section................................................... 4 Changes to Figure 13 ...................................................................... 21 Changes to Equation 18.................................................................. 24 Changes to Equation ...
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AD9879 SPECIFICATIONS V = 3.3 V ± 5 3.3 V ± 10 4.02 kΩ, 75 Ω DAC load, unless otherwise noted. SET Table 1. Parameter OSCIN AND XTAL CHARACTERISTICS Frequency Range Duty Cycle ...
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Parameter 10-BIT ADC CHARACTERISTICS Resolution Maximum Conversion Rate Pipeline Delay Analog Input Input Voltage Range Input Capacitance Differential Input Resistance Reference Voltage Error (REFT10–REFB10) – Performance (A = –0.5 dBFS MHz ADC Sample ...
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AD9879 Parameter Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) CHANNEL-TO-CHANNEL ISOLATION Tx DAC-to-ADC Isolation ( MHz) OUT Isolation Between Tx and IQ ADCs Isolation Between Tx and 10-Bit ADC Isolation Between Tx and 12-Bit ...
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ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Power Supply ( AVDD DVDD DRVDD Digital Output Current Digital Inputs Analog Inputs Operating Temperature Maximum Junction Temperature Storage Temperature Lead Temperature (Soldering, 10 sec) Stresses above those listed under Absolute ...
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AD9879 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DNC 1 DRGND 2 DRVDD 3 IF(11) 4 IF(10) 5 IF(9) 6 IF(8) 7 IF(7) 8 IF(6) 9 IF(5) 10 IF(4) 11 IF(3) 12 IF(2) 13 IF(1) 14 IF(0) 15 RXIQ(3) 16 RXIQ(2) 17 ...
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Pin No. Mnemonic 41 SCLK SDIO 44 SDO 45 DGNDTX 46 DVDDTX 47 PWRDN 48 REFIO 49 FSADJ 50 AGNDTX 51, 52 TX−, TX+ 53 AVDDTX 54 DGNDPLL 55 DVDDPLL 56 AVDDPLL 57 PLLFILT 58 AGNDPLL 59 ...
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AD9879 TERMINOLOGY Aperture Delay The aperture delay is a measure of the sample-and-hold amplifier (SHA) performance. It specifies the time delay between the rising edge of the sampling clock input and when the input signal is held for conversion. Aperture ...
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THEORY OF OPERATION To gain a general understanding of the AD9879, refer to the block diagram of the device architecture in Figure 3. The device consists of a transmit path, receive path, and auxiliary functions, such as a DPLL, a ...
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AD9879 INTERPOLATION FILTER Once through the data assembler, the IQ data streams are fed through a 4× FIR low-pass filter and a 4× cascaded integrator- comb (CIC) low-pass filter. The combination of these two filters results in the sample rate ...
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An internal PLL generates the DAC sampling frequency multiplying OSCIN frequency M times. The MCLK signal (Pin 23 derived by dividing f MCLK SYSCLK × M SYSCLK OSCIN × ...
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AD9879 RESET AND TRANSMIT POWER-DOWN Power-Up Sequence On initial power-up, the RESET pin should be held low until the power supply is stable. Once RESET is deasserted, the AD9879 can be programmed over the serial port. The on-chip PLL requires ...
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OUTPUTS The AD9879 contains an on-chip Σ-Δ output that provides a digital logic bit stream with an average duty cycle that varies between 0% and (4095/4096)%, depending on the programmed code, as shown in Figure 7. This bit stream ...
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AD9879 REGISTER MAP AND BIT DEFINITIONS 1 Table 4. Register Map Address (hex) Bit 7 Bit 6 0x00 SDIO SPI Bytes Bidirectional LSB First 0x01 PLL Lock Detect 0x02 Power- Power- Down PLL Down DAC Tx 0x03 Σ-∆ Output Control ...
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REGISTER 0x00—INITIALIZATION Bits 0–4: OSCIN Multiplier This register field is used to program the on-chip multiplier (PLL) that generates the chip’s high frequency system clock f . The value of M depends on the ADC clocking mode SYSCLK selected, as ...
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AD9879 The default value for the clamp level control value is 0x20. This results in an ADC output clamp level offset of 512 LSBs. The valid programming range for the clamp level control value is from 0x16 to 0x127. REGISTER ...
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Bit 5: Tx Path Select Profile 1 The AD9879 quadrature digital upconverter is capable of storing two preconfigured modulation modes called profiles. Each profile defines a transmit frequency tuning word and cable driver amplifier gain (DAC gain) setting. The profile ...
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AD9879 SERIAL INTERFACE FOR REGISTER CONTROL The AD9879 serial port is a flexible, synchronous serial communication port that allows easy interface to many industry-standard microcontrollers and microprocessors. The interface allows read/write access to all registers that configure the AD9879. Single ...
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When this bit is set default low, the AD9879 serial port is in MSB-first format. In MSB-first mode, the instruction byte and data bytes must be written from the MSB to the LSB. In MSB- first mode, the serial port ...
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AD9879 TRANSMIT PATH (TX) MCLK TXSYNC TXI[11:6] TXI[5:0] TXIQ TRANSMIT TIMING The AD9879 provides a master clock, MCLK, and expects 6-bit multiplexed TxIQ data upon each rising edge. Transmit symbols are framed with the TxSYNC input. TxSYNC high indicates the ...
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FREQUENCY RELATIVE TO I/Q NYQUIST BW Figure 15. Cascaded Filter Pass-Band Detail ( keep the bandwidth of the data in the flat ...
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AD9879 Tx SIGNAL LEVEL CONSIDERATIONS The quadrature modulator introduces a maximum gain signal level. To visualize this, assume that both the I data and Q data are fixed at the maximum possible digital value, x. The ...
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DIGITAL-TO-ANALOG CONVERTER A 12-bit digital-to-analog converter (DAC) is used to convert the digitally processed waveform into an analog signal. The worst-case spurious signals due to the DAC are the harmonics of the fundamental signal and their aliases. The conversion process ...
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AD9879 PROGRAMMING THE AD8321/AD8323 OR AD8322/AD8327 CABLE DRIVER AMPLIFIER GAIN CONTROL Programming the gain of the AD832x family of cable driver amplifiers can be accomplished via the AD9879 cable amplifier control interface. Four 8-bit registers within the AD9879 (one per ...
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RECEIVE PATH (Rx) IF10 AND IF12 ADC OPERATION The IF10 and IF12 ADCs have a common architecture and share many of the same characteristics from an applications standpoint. Most of the information in this section is applicable to both IF ...
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AD9879 PCB DESIGN CONSIDERATIONS Although the AD9879 is a mixed-signal device, the part should be treated as an analog component. The on-chip digital circuitry is specially designed to minimize the impact the digital switching noise has on the operation of ...
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GROUND PLANES In general, if the component placing guidelines discussed in the Component Placement section can be implemented best to have at least one continuous ground plane for the entire board. All ground connections should be made as ...
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... AD9879 OUTLINE DIMENSIONS 2.90 2.70 2.50 0.50 0.25 VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range AD9879BS −40°C to +85°C 1 AD9879BSZ −40°C to +85°C AD9879- Pb-free part. 23.20 BSC 20.00 BSC 3.40 1.03 MAX 18.85 REF 0.88 0. SEATING ...
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NOTES Rev Page AD9879 ...
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AD9879 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02773-0-6/05(A) Rev Page ...