MAX5865ETM+T Maxim Integrated Products, MAX5865ETM+T Datasheet - Page 18

• Manufacturer Part Number: MAX5865ETM+T
• Description: IC ANLG FRONT END 40MSPS 48-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX5865ETM+T

• Number Of Bits: 10
• Number Of Channels: 4
• Power (watts): 2.10W
• Voltage - Supply, Analog: 2.7 V ~ 3.3 V
• Voltage - Supply, Digital: 1.8 V ~ 3.3 V
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ultra-Low-Power, High-Dynamic-
Performance, 40Msps Analog Front End
Figure 5. 3-Wire Serial Interface Timing Diagram
Figure 6. MAX5865 Mode Recovery Timing Diagram
Figure 6
t
or standby mode and entering into Rx, Tx, or Xcvr
mode. t
between any Rx, Tx, or Xcvr mode. t
the time for the ADC to settle within 1dB of specified
SINAD performance and DAC settling to 10 LSB error.
t
serial command is latched into the MAX5865 by CS
transition high. t
the DAC wake-up time. The recovery time is 10µs to
switch between Xcvr, Tx, or Rx modes. The recovery
time is 40µs to switch from shutdown or standby mode
to Xcvr mode.
18
WAKE
WAKE
SCLK
DIN
CS
______________________________________________________________________________________
DAO–DA7
is the wake-up time when exiting shutdown, idle,
ID/QD
or t
SCLK
ENABLE
DIN
CS
shows the mode recovery timing diagram.
ENABLE
t
CSS
ENABLE
is the recovery time when switching
times are measured after the 8-bit
t
DS
for Xcvr mode is dominated by
MSB
t
DH
Mode Recovery Timing
t
CP
8-BIT DATA
WAKE
or t
t
CH
ENABLE
is
CLK input is shared by both the ADCs and DACs. It
accepts a CMOS-compatible signal level set by OV
from 1.8V to V
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). Specifically,
sampling occurs on the rising edge of the clock signal,
requiring this edge to provide the lowest possible jitter.
Any significant clock jitter limits the SNR performance
of the on-chip ADCs as follows:
where f
t
AJ
is the time of the clock jitter.
IN
t
WAKE, SD, ST_ (Rx)
SNR
represents the analog input frequency and
DD
=
t
. Since the interstage conversion of the
WAKE, SD, ST_ (Tx)
20
OR t
×
System Clock Input (CLK)
ENABLE, Rx
log
t
CL
ADC DIGITAL OUTPUT.
SINAD SETTLES WITHIN 1dB



OR t
2
ENABLE
×
DAC ANALOG OUTPUT. OUTPUT
SETTLES TO 10 LSB ERROR
π
×
LSB
T
X
1
t
t
IN
CS
×
t
AJ



t
CSW
DD