ISL98003INZ-110 Intersil, ISL98003INZ-110 Datasheet - Page 23

• Manufacturer Part Number: ISL98003INZ-110
• Description: IC AFE 3CH 8BIT 110MHZ 80EPTQFP
• Manufacturer: Intersil

Specifications of ISL98003INZ-110

• Number Of Bits: 8
• Number Of Channels: 3
• Power (watts): 1.1W
• Voltage - Supply, Analog: 1.8V, 3.3V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SOG
For component YPbPr signals, the sync signal is embedded
on the Y channel’s video, which is connected to the green
input, hence the name SOG (Sync on Green). The horizontal
sync information is encoded onto the video input by adding
the sync tip during the blanking interval. The sync tip level is
typically 0.3V below the video black level.
To minimize the loading on the green channel, the SOG input
for each of the green channels should be AC-coupled to the
ISL98003 through a series combination of a 10nF capacitor
and a 500Ω resistor.
SOG Slicer
The SOG input has programmable threshold, 40mV of
hysteresis, and an optional low pass filter than can be used
to remove high frequency video spikes (generated by
overzealous video peaking in a DVD player, for example)
that can cause false SOG triggers. The SOG threshold sets
the comparator threshold relative to the sync tip (the bottom
of the SOG pulse).
Inside the ISL98003, a 1µA pull-down ensures that each sync
tip triggers the clamp circuit causing the tip to be clamped to a
600mV level. A comparator compares the SOG signal with an
internal 4-bit programmable threshold level reference ranging
from 0mV to 300mV above the sync clamp level. The SOG
threshold level, hysteresis, and low-pass filter is programmed
via registers 0x30and 0x31. If the Sync-On-Green function is
not needed, the SOG
SYNC Processing
The ISL98003 can process sync signals from 3 different
sources: discrete HSYNC and VSYNC, composite sync on
the HSYNC input, or composite sync from a Sync-On-Green
(SOG) signal embedded on the Green video input. The
ISL98003 has SYNC activity detect functions to help the
firmware determine which sync source is available.
R(GB)
R(GB)
R(GB)
R(GB)
GND
GND
IN
IN
0
0
1
1
(Figure 2)
DC Restore
Clamp DAC
VGA0
VGA1
IN
pin(s) may be left unconnected.
V
V
IN
IN
DC Restoration
+
-
V
CLAMP
23
PGA
GENERATION
CLAMP
FIGURE 1. VIDEO FLOW (INCLUDING ABLC™)
Bandwidth
Input
Bandwidth
Control
ABLC
Block
To
ISL98003
Macrovision
The ISL98003 automatically detects the presence of
Macrovision-encoded video. When Macrovision is detected,
it generates a mask signal that is ANDed with the incoming
SOG CSYNC signal to remove the Macrovision before the
HSYNC goes to the PLL. No additional programming is
required to support Macrovision.
The mask signal is also applied to the HSYNC
When Sync Mask Disable = 0, any Macrovision present on
the incoming sync will not be visible on HSYNC
application requires the Macrovision pulses to be visible on
HSYNC
0x7A bit 4).
Headswitching from Analog Videotape Signals
Occasionally this AFE may be used to digitize signals
coming from analog videotape sources. The most common
example of this is a Digital VCR (which for best signal quality
would be connected to this AFE with a component YPbPr
connection). If the digital VCR is playing an older analog
VHS tape, the sync signals from the VCR may contain the
worst of the traditional analog tape artifacts: headswitching.
Headswitching is traditionally the enemy of PLLs with large
capture ranges, because a headswitch can cause the
HSYNC period to change by as much as ±90%. To the PLL,
this can look like a frequency change of -50% to +900%,
causing errors in the output frequency (and obviously the
phase) to change. Subsequent HSYNCs have the correct,
original period, but most analog PLLs will take dozens of
lines to settle back to the correct frequency and phase after
a headswitch disturbance. This causes the top of the image
to “tear” during normal playback. In “trick modes” (fast
forward and rewind), the HSYNC signal has multiple
headswitch-like discontinuities, and many PLLs never settle
to the correct value before the next headswitch, rendering
the image completely unintelligible.
Offset
DAC
Compensation (ABLC™ ) Loop
OUT
10
8 bit ADC
Automatic Black Level
ABLC™
, set the HSYNC
Offset
Fixed
10
10
Vref
ABLC™
OUT
8
Mask Disable bit (register
Registers
Control
Offset
ABLC™
10
8
10
Offset
Fixed
0x000
8
OUT
September 12, 2008
OUT
To Output
Formatter
signal.
. If the
FN6760.0