MAX19707ETM+ Maxim Integrated Products, MAX19707ETM+ Datasheet
MAX19707ETM+
Specifications of MAX19707ETM+
Related parts for MAX19707ETM+
MAX19707ETM+ Summary of contents
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... Portable Communication Equipment Ordering Information PART* PIN-PACKAGE MAX19707ETM 48 Thin QFN-EP** MAX19707ETM+ 48 Thin QFN-EP** *All devices are specified over the -40°C to +85°C operating range. **EP = Exposed paddle. +Denotes lead-free package. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’ ...
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Ultra-Low-Power Analog Front-End ABSOLUTE MAXIMUM RATINGS GND OGND ..............................-0.3V to +3.6V GND to OGND.......................................................-0.3V to +0.3V IAP, IAN, QAP, QAN, IDP, IDN, QDP, QDN, DAC1, DAC2, DAC3 to GND .....................-0. ...
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ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output 0.33µF, unless otherwise noted. C ...
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Ultra-Low-Power Analog Front-End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output ...
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ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output 0.33µF, unless otherwise noted. C ...
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Ultra-Low-Power Analog Front-End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output ...
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ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output 0.33µF, unless otherwise noted. C ...
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Ultra-Low-Power Analog Front-End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output ...
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ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output 0.33µF, unless otherwise noted. C ...
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Ultra-Low-Power Analog Front-End ( 1.8V, internal reference (1.024V amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output 0.33µ ...
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OV = 1.8V, internal reference (1.024V amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output 0.33µ +25°C, unless otherwise noted.) COM ...
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Ultra-Low-Power Analog Front-End ( 1.8V, internal reference (1.024V amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output 0.33µ ...
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OV = 1.8V, internal reference (1.024V amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output 0.33µ +25°C, unless otherwise noted.) COM ...
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Ultra-Low-Power Analog Front-End ( 1.8V, internal reference (1.024V amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output 0.33µ ...
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PIN NAME 10 QAP Channel-QA Positive Analog Input. For single-ended operation, connect signal source to QAP. Digital I/O. Outputs for receive ADC in Rx mode. Inputs for transmit DAC in Tx mode the most 13–18, 21–24 D0–D9 significant ...
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Ultra-Low-Power Analog Front-End Dual, 10-Bit Rx ADC The ADC uses a seven-stage, fully differential, pipelined architecture that allows for high-speed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half ...
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Table 1. Rx ADC Output Codes vs. Input Voltage DIFFERENTIAL INPUT DIFFERENTIAL INPUT (LSB) VOLTAGE V x 512/512 511 (+Full Scale - 1 LSB) REF V x 511/512 510 (+Full Scale - 2 LSB) REF V x 1/512 REF V ...
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Ultra-Low-Power Analog Front-End CHI CHQ t CLK CLK t t DOQ DOI D0–D9 D0Q D1I D1Q Figure 3. Rx ADC System Timing Diagram Dual, 10-Bit Tx DAC The dual, 10-bit digital-to-analog converter (Tx DAC) ...
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The Tx DAC also features independent DC offset cor- rection of each I/Q channel. This feature is configured through the SPI interface. The DC offset correction is MAX19707 Tx DAC I-CH Tx DAC Q-CH FULL SCALE = 1.25V V = ...
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Ultra-Low-Power Analog Front-End Figure 5 shows the relationship between the clock, input data, and analog outputs. Data for the I channel (ID) is latched on the falling edge of the clock signal, and Q- channel (QD) data is ...
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Table 3. MAX19707 Mode Control D11 D10 REGISTER NAME (MSB) 15 E11 = 0 E10 = 0 ENABLE-16 Reserved Reserved Aux-DAC1 1D11 1D10 Aux-DAC2 2D11 2D10 Aux-DAC3 3D11 3D10 IOFFSET — — QOFFSET — — COMSEL — — AD11 = ...
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Ultra-Low-Power Analog Front-End Table 5. External Tx-Rx Control Using ADDRESS DATA BITS 0011 0100 0000 (16-Bit Mode) or 1000 (8-Bit Mode) 0101 0110 22 ______________________________________________________________________________________ T/R Pin (T ...
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Table 6. Tx-Rx Control Using SPI Commands ADDRESS DATA BITS 1011 1100 0000 (16-Bit Mode) or 1000 (8-Bit Mode) 1101 1110 X = Don’t care. In ENABLE-16 mode, the aux-DACs have independent ...
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Ultra-Low-Power Analog Front-End Table 9. Offset Control Bits for I and Q Channels (IOFFSET or QOFFSET Mode) BITS IO5–IO0 WHEN IN IOFFSET MODE, BITS QO5–QO0 WHEN IN QOFFSET MODE IO5/QO5 IO4/QO4 • ...
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However, power consumption is higher in this mode because both the Tx and Rx cores are always on. To prevent bus contention in these states, the Rx ADC out- put buffers are tri-stated during Tx and the Tx DAC input ...
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Ultra-Low-Power Analog Front-End Mode-Recovery Timing Figure 7 shows the mode-recovery timing diagram the wakeup time when exiting shutdown, idle, WAKE or standby mode and entering mode the recovery time when switching ...
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Auxiliary Control DACs The MAX19707 includes three 12-bit aux-DACs (DAC1, DAC2, DAC3) with 1µs settling time for controlling VGA, AGC, and AFC functions. The aux-DAC output range is 0.1V to 2.56V. During power-up, the VGA and AGC out- puts ...
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Ultra-Low-Power Analog Front-End The conversion requires 12 clock edges (1 for input sampling, 1 for each of the 10 bits, and 1 at the end for loading into the serial output register) to complete one conversion cycle (when ...
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Table 17. Reference Modes V REFIN Internal Reference Mode. V > 0. with a 0.33µF capacitor. Buffered External Reference Mode. An external 1.024V ±10% reference voltage is applied to REFIN. V 1.024V ±10% internally generated to be ...
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Ultra-Low-Power Analog Front-End IDP MAX19707 IDN QDP QDN Figure 9. Balun Transformer-Coupled Differential-to-Single- Ended Output Drive for Tx DAC REFP 1kΩ ISO IN 0.1μF 50Ω 22pF 100Ω 1kΩ REFN 0.1μF R ISO 50Ω 100Ω ...
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R1 600Ω R2 600Ω R3 600Ω Figure 11. Rx ADC DC-Coupled Differential Drive 802.11X ZIF TRANSCEIVER AGC TCXO BATTERY VOLTAGE MONITOR TEMPERATURE MEASURE Figure 12. Typical Application Circuit for 802.11 Radio ______________________________________________________________________________________ 10-Bit, 45Msps, Ultra-Low-Power R4 R5 600Ω 600Ω R ...
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Ultra-Low-Power Analog Front-End Grounding, Bypassing, and Board Layout The MAX19707 requires high-speed board layout design techniques. Refer to the MAX19707 EV kit data sheet for a board layout reference. Place all bypass capacitors as close to the device ...
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Ideally, the ADC full-scale transition occurs at 1.5 LSB below full scale. The gain error is the amount of devia- tion between the measured transition point and the ideal transition point with the offset error removed. ADC Dynamic Parameter Definitions ...
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Ultra-Low-Power Analog Front-End Power-Supply Rejection Power-supply rejection is defined as the shift in offset and gain error when the power supply is changed ±5%. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ADC in ...
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Ultra-Low-Power V = 2.7V TO 3.3V DD IAP 10-BIT IAN QAP 10-BIT ADC QAN IDP 10-BIT DAC IDN QDP 10-BIT DAC QDN PROGRAMMABLE OFFSET/CM 12-BIT DAC1 12-BIT DAC2 12-BIT DAC3 ADC1 ADC2 4:1 MUX ...
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Ultra-Low-Power Analog Front-End (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) E E/2 D ______________________________________________________________________________________ DETAIL A e (ND- ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 37 © 2007 Maxim Integrated Products ...