DS1742W-120+ Maxim Integrated Products, DS1742W-120+ Datasheet - Page 5

• Manufacturer Part Number: DS1742W-120+
• Description: IC RTC RAM Y2K 3.3V 120NS 24EDIP
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/NVSRAM/Y2Kr

Specifications of DS1742W-120+

• Memory Size: 16K (2K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (600 mil) Module
• Function: Clock/Calendar/NV Timekeeping RAM
• Rtc Memory Size: 2048 Byte
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 2.97 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Rtc Bus Interface: Parallel
• Supply Current: 15 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RETRIEVING DATA FROM RAM OR CLOCK
The DS1742 is in the read mode wheneve
high, and
of the address locations in the NV SRAM. Valid data will be available at the DQ pins within t
after the last address input is stable, providing that the
satisfied. If
latter of chip enable access (t
input/output pins (DQ) is controlled by
data lines are driven to an intermediate state until t
go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1742 is in the write mode whenever
write is referenced to the latter occurring transition of
valid throughout the cycle.
initiation of another read or write cycle. Data in must be valid t
remain valid for t
cycle. However,
contention. If
data defined by the address inputs. A low transition on
after
DATA RETENTION MODE
The 5V device is fully accessible and data can be written or read only when V
V
occurs) the internal clock registers and SRAM are blocked from any access. When V
below the battery switch point V
pin to the backup battery. RTC operation and SRAM data are maintained from the battery until
V
read only when V
the device is inhibited. If V
backup supply (V
switched from V
SRAM data are maintained from the battery until V
CE
PF
CC
.
is returned to nominal levels. The 3.3V device is fully accessible and data can be written or
and
However, when V
WE
OE
goes active.
CE
remain valid, output data will remain valid for output data hold time (t
CE
OE
(chip enable) is low. The device architecture allows ripple-through access to any
or
CC
DH
OE
BAT
is low prior to
CC
to the backup supply (V
OE
is greater than V
afterward. In a typical application, the
) when V
can be active provided that care is taken with the data bus to avoid bus
access times and states are not met, valid data will be available at the
CC
is below the power fail point, V
PF
CE
CC
CEA
is less than Vso
SO
drops below V
or
WE
) or at output enable access time (t
(battery supply level), device power is switched from the V
WE
transitioning low the data bus can become active with read
PF
.
When V
CE
must return inactive for a minimum of t
, and
BAT
r
WE
5 of 16
)
OE
PF
CC
,
when V
.
OE
the device power is switched from V
and
If V
falls below the power fail point, V
CC
(output enable) is low,
. If the outputs are activated before t
AA
is returned to nominal levels.
PF
. If the address inputs are changed while
CE
WE
CC
C E
is greater than Vso
are in their active state. The start of a
WE
drops below Vso
on
and
OE
PF
,
will then disable the outputs t
CE
signal will be high during a write
(point at which write protection
OE
DS
. The addresses must be held
prior to the end of write and
access times and states are
OEA
). The state of the data
WE
,
.
the device power is
RTC operation and
CC
(write enable) is
OH
WR
is greater than
) but will then
PF
prior to the
,
access to
CC
DS1742
AA
CC
to the
, the
falls
WEZ
AA
CC