DS1742W-120+ Maxim Integrated Products, DS1742W-120+ Datasheet - Page 3

• Manufacturer Part Number: DS1742W-120+
• Description: IC RTC RAM Y2K 3.3V 120NS 24EDIP
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/NVSRAM/Y2Kr

Specifications of DS1742W-120+

• Memory Size: 16K (2K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (600 mil) Module
• Function: Clock/Calendar/NV Timekeeping RAM
• Rtc Memory Size: 2048 Byte
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 2.97 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Rtc Bus Interface: Parallel
• Supply Current: 15 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CLOCK OPERATIONS—READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data,
internal updates to the DS1742 clock registers should be halted before clock data is read to
prevent reading of data in transition. However, halting the internal clock register updating
process does not affect clock accuracy. Updating is halted when a 1 is written into the read bit,
bit 6 of the century register, see Table 2. As long as a 1 remains in that position, updating is
halted. After a halt is issued, the registers reflect the count, that is day, date, and time that was
current at the moment the halt command was issued. However, the internal clock registers of
the double-buffered system continue to update so that the clock accuracy is not affected by the
access of data. All of the DS1742 registers are updated simultaneously after the internal clock
register updating process has been re-enabled. Updating is within a second after the read bit is
written to 0. The READ bit must be a zero for a minimum of 500s to ensure the external
registers will be updated.
Figure 1. DS1742 BLOCK DIAGRAM
Table 1. TRUTH TABLE
V
V
SO
CC
V
< V
< V
CC
V
> V
CC
CC
SO
< V
< V
PF
PF
PF
V
V
V
V
CE
X
X
IH
IL
IL
IL
V
OE
V
X
X
X
X
IH
IL
WE
V
V
V
X
X
X
IH
IH
IL
Deselect
Deselect
Deselect
MODE
Write
Read
Read
3 of 16
Data Out
Data In
High-Z
High-Z
High-Z
High-Z
DQ
Data Retention Mode
CMO
POWER
Standby
Active
Active
Active
S Stan
dby
DS1742