DS1554-70IND+ Maxim Integrated Products, DS1554-70IND+ Datasheet - Page 5

• Manufacturer Part Number: DS1554-70IND+
• Description: IC RTC RAM Y2K 5V 70NS 32-EDIP
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/NVSRAM/Y2Kr

Specifications of DS1554-70IND+

• Memory Size: 256K (32K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 32-DIP Module (600 mil), 32-EDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DATA-READ MODE
The DS1554 is in the read mode whenever CE (chip enable) is low and WE (write enable) is high. The
device architecture allows ripple-through access to any valid address location. Valid data will be available
at the DQ pins within t
satisfied. If CE or OE access times are not met, valid data will be available at the latter of chip enable
access (t
controlled by CE and OE. If the outputs are activated before t
intermediate state until t
will remain valid for output data hold time (t
access.
DATA-WRITE MODE
The DS1554 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout the
cycle. CE and WE must return inactive for a minimum of t
or write cycle. Data in must be valid t
a typical application, the OE signal will be high during a write cycle. However, OE can be active
provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
transitioning low, the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs t
DATA-RETENTION MODE
The 5V device is fully accessible and data can be written and read only when V
However, when V
internal clock registers and SRAM are blocked from any access. When V
point V
battery. RTC operation and SRAM data are maintained from the battery until V
levels.
The 3.3V device is fully accessible and data can be written and read only when V
When V
switched from V
than V
below V
nominal levels.
All control, data, and address signals must be powered down when V
SO
SO
CC
CEA
, the device power is switched from V
SO
(battery supply level), device power is switched from the V
. RTC operation and SRAM data are maintained from the battery until V
falls below V
) or at output enable access time (t
CC
CC
to the internal backup lithium battery when V
is below the power-fail point V
AA
AA
PF
after the last address input is stable, providing that CE and OE access times are
. If the address inputs are changed while CE and OE remain valid, output data
, access to the device is inhibited. If V
DS
prior to the end of the write and remain valid for t
OH
WEZ
CC
DS1554 256k, Nonvolatile, Y2K-Compliant Timekeeping RAM
) but will then go indeterminate until the next address
5 of 18
OEA
to the internal backup lithium battery when V
after WE goes active.
). The state of the data input/output pins (DQ) is
PF
(point at which write protection occurs) the
WR
prior to the initiation of a subsequent read
PF
CC
AA
is less than V
CC
CC
, the data lines are driven to an
drops below V
is powered down.
pin to the internal backup lithium
CC
falls below the battery switch
CC
SO
CC
CC
is returned to nominal
, the device power is
PF
is greater than V
is greater than V
. If V
CC
DH
is returned to
afterward. In
PF
is greater
CC
drops
PF
PF
.
.