DS3232S#T&R Maxim Integrated Products, DS3232S#T&R Datasheet - Page 17

• Manufacturer Part Number: DS3232S#T&R
• Description: IC RTC W/TCXO 20-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/TCXO/Crystalr

Specifications of DS3232S#T&R

• Memory Size: 236B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 3. Data Write—Slave Receiver Mode
Figure 4. Data Read—Slave Transmitter Mode
Figure 5. Data Write/Read (Write Pointer, Then Read)—Slave Receive and Transmit
the slave address. Next follows a number of data
bytes. The slave returns an acknowledge bit after
each received byte. Data is transferred with the most
significant bit (MSB) first.
Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is trans-
mitted by the master. The slave then returns an
acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The
master returns an acknowledge bit after all received
S - START
A - ACKNOWLEDGE (ACK)
P - STOP
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
S - START
A - ACKNOWLEDGE (ACK)
P - STOP
A - NOT ACKNOWLEDGE (NACK)
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
S
S
ADDRESS>
ADDRESS>
1101000
1101000
<SLAVE
<SLAVE
S - START
Sr - REPEATED START
A - ACKNOWLEDGE (ACK)
P - STOP
A - NOT ACKNOWLEDGE (NACK)
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
XXXXXXXX
<DATA (n)>
S
0
1
<R/W>
<R/W>
ADDRESS>
1101000
<SLAVE
A
A
<WORD ADDRESS (n)>
MASTER TO SLAVE
<R/W>
A
XXXXXXXX
<DATA (n)>
XXXXXXXX
SLAVE TO MASTER
0
Extremely Accurate I
A
<DATA (n + 1)>
____________________________________________________________________
XXXXXXXX
<WORD ADDRESS (n)>
MASTER TO SLAVE
XXXXXXXX
A
A
Integrated Crystal and SRAM
<DATA (n + 1)>
SLAVE TO MASTER
A
XXXXXXXX
XXXXXXXX
<DATA (n)>
MASTER TO SLAVE
A
<DATA (n + 2)>
<SLAVE ADDRESS (n)>
XXXXXXXX
Sr
SLAVE TO MASTER
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
1101000
A
A
bytes other than the last byte. At the end of the last
received byte, a not acknowledge is returned.
The master device generates all the serial clock puls-
es and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated
START condition. Since a repeated START condition
is also the beginning of the next serial transfer, the
bus will not be released. Data is transferred with the
most significant bit (MSB) first.
(X + 1 BYTES + ACKNOWLEDGE)
(X + 1 BYTES + ACKNOWLEDGE)
<DATA (n + 2)>
<DATA (n + 1)>
A
XXXXXXXX
XXXXXXXX
DATA TRANSFERRED
<R/W>
1
DATA TRANSFERRED
...
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
A
<DATA (n + X)>
XXXXXXXX
(X + 1 BYTES + ACKNOWLEDGE)
A
A
DATA TRANSFERRED
...
...
2
<DATA (n + X)>
<DATA (n + X)
A
XXXXXXXX
XXXXXXXX
C RTC with
P
A
A
P
P
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