ISL12058IRTZ Intersil, ISL12058IRTZ Datasheet - Page 10

• Manufacturer Part Number: ISL12058IRTZ
• Description: IC RTC/CALENDAR I2C-BUS 8-TDFN
• Manufacturer: Intersil
• Type: Clock/Calendar/Alarmr

Specifications of ISL12058IRTZ

• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TDFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

24 HOUR TIME
If the MIL bit of the HR register is “1”, the RTC uses a
24-hour format. If the MIL bit is “0”, the RTC uses a 12-hour
format and HR21 bit functions as an AM/PM indicator with a
“1” representing PM. The clock defaults to 12-hour format
time with HR21 = “0”.
If the A1HR and/or A2HR registers are used for alarm
interrupt, the A1HR and/or A2HR registers must set to the
same hour format as the HR register. For example, if the HR
register is set to 24-hour format by setting the MIL bit to “1”,
then the AxHR register must be set to 24-hour format with
AxMIL bit set to “1”. If the hour format does not match
between the HR register and the AxHR register, then the
alarm interrupt will not trigger.
LEAP YEARS
Leap years add the day February 29 and are defined as those
years that are divisible by 4. Years divisible by 100 are not leap
years, unless they are also divisible by 400. This means that
the year 2000 is a leap year, the year 2100 is not. The
ISL12058 does not correct for the leap year in the year 2100.
Control and Status Registers
Addresses [07h to 0Bh]
The Control and Status Registers consist of the Status
Register, Interrupt Register, and Alarm Registers.
Status Register (SR) [Address 07h]
The Status Register is located in the memory map at
address 0Bh. This is a volatile register that provides either
control or status of alarm interrupt and crystal oscillator
enable. Refer to Table 2.
NOTE: read operation will remain set after the read operation is
complete.
POWER FAILURE BIT (PF)
This bit is set to a “1” after a total power failure. This is a read
only bit that is set by hardware (ISL12058 internally) when
the device powers up after having lost power to the device.
On power-up after a total power failure, all registers are set
to their default states. The first valid write to the RTC section
after a complete power failure resets the PF bit to “0” (writing
one RTC register is sufficient).
ALARM1 INTERRUPT BIT (A1F)
These bits announce if the Alarm1 matches the real time
clock. If there is a match, the respective bit is set to “1”. This
bit is manually reset to “0” by the user. A write to this bit in
the SR can only set it to “0”, not “1”.
Default
ADDR
07h
ARST
7
0
TABLE 2. STATUS REGISTER (SR)
XSTOP
6
0
5
0
0
10
WRTC OSF A1F A2F
4
0
3
1
2
0
1
0
PF
0
1
ISL12058
ALARM2 INTERRUPT BIT (A2F)
These bits announce if the Alarm2 matches the real time
clock. If there is a match, the respective bit is set to “1”. This
bit is manually reset to “0” by the user. A write to this bit in
the SR can only set it to “0”, not “1”.
OSCILLATOR FAIL BIT (OSF)
Oscillator Fail Indicator bit (OSF). This bit is set to a “1” when
there is no oscillation on X1 pin. The OSF bit can only be
reset by having an oscillation on X1 and manually reset to
“0” to reset it.
WRITE RTC ENABLE BIT (WRTC)
The WRTC bit enables or disables write capability into the
RTC Timing Registers. The factory default setting of this bit
is “0”. Upon initialization or power-up, the WRTC must be set
to “1” to enable the RTC. Upon the completion of a valid
write (STOP), the RTC starts counting. The RTC internal
1Hz signal is synchronized to the STOP condition during a
valid write cycle.
CRYSTAL OSCILLATOR ENABLE BIT (XSTOP)
This bit enables/disables the internal crystal oscillator. When
the XSTOP is set to “1”, the oscillator is disabled. The
XSTOP bit is set to “0” on power-up for normal operation.
AUTO RESET ENABLE BIT (ARST)
This bit enables/disables the automatic reset of the A1F and
A2F status bits only. When ARST bit is set to “1”, these
status bits are reset to “0” after a valid read of the respective
status register (with a valid STOP condition). When the
ARST is cleared to “0”, the user must manually reset the
A1F and A2F bits.
Interrupt Control Register (INT) [Address 08h]
ALARM1 INTERRUPT ENABLE BIT (A1E)
This bit enables the hardware interrupt function of ALARM1
to IRQ/F
ALM1E set to ‘1’, the IRQ/F
A1F bit is set by the ALARM1 interrupt.
IRQ/F
This bit selects the function of the IRQ/F
Table 4 for function selection of IRQ/F
08h
Default
ADDR
A1E
TABLE 4. FUNCTION SELECTION OF IRQ/F
0
0
OUT
TABLE 3. INTERRUPT CONTROL REGISTER (INT)
OUT
7
0
0
IRQE
FUNCTION SELECTION BIT (IRQE)
0
1
A1E AND IRQE BITS
pin. When A1E set to ‘1’, IRQE set to ‘1’ and
ALM1E
6
0
ALM2E
5
0
OUT
IRQ/F
High Impedance
pin will pull low when the
FO1 FO0 IRQE
OUT
4
1
F
OUT
OUT
FUNCTION
3
1
OUT
PIN.
OUT
pin. Refer to
2
0
PIN WITH
June 15, 2009
1
0
0
FN6756.0
A1E
0
0