DS1305N+ Maxim Integrated Products, DS1305N+ Datasheet - Page 7

• Manufacturer Part Number: DS1305N+
• Description: IC RTC SERIAL ALARM 16-DIP
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/Alarmr

Specifications of DS1305N+

• Memory Size: 96B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Function: Clock/Calendar/Alarm
• Rtc Memory Size: 96 Byte
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: Through Hole
• Rtc Bus Interface: Serial (3-Wire, SPI)
• Supply Current: 1.28 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

hour, and minute alarm registers is set to a logic 1. When bit 7 of the day, hour, minute, and seconds
alarm registers is set to a logic 1, alarm occurs every second.
During each clock update, the RTC compares the Alarm 0 and Alarm 1 registers with the corresponding
clock registers. When a match occurs, the corresponding alarm flag bit in the status register is set to a 1. If
the corresponding alarm interrupt enable bit is enabled, an interrupt output is activated.
Table 2. TIME-OF-DAY ALARM MASK BITS
SPECIAL PURPOSE REGISTERS
The DS1305 has three additional registers (control register, status register, and trickle charger register)
that control the RTC, interrupts, and trickle charger.
CONTROL REGISTER (READ 0Fh, WRITE 8Fh)
logic 1, the oscillator is stopped and the DS1305 is placed into a low-power standby mode with a current
drain of less than 100nA when power is supplied by V
will be set to a logic 1.
WP (Write Protect) – Before any write operation to the clock or RAM, this bit must be logic 0. When
high, the write protect bit prevents a write operation to any register, including bits 0, 1, 2, and 7 of the
control register. Upon initial power-up, the state of the WP bit is undefined. Therefore, the WP bit should
be cleared before attempting to write to the device.
INTCN (Interrupt Control) – This bit controls the relationship between the two time-of-day alarms and
the interrupt output pins. When the INTCN bit is set to a logic 1, a match between the timekeeping
registers and the Alarm 0 registers activates the
match between the timekeeping registers and the Alarm 1 registers activate the
the alarm is enabled). When the INTCN bit is set to a logic 0, a match between the timekeeping registers
and either Alarm 0 or Alarm 1 activate the
function when INTCN is set to a logic 0.
AIE0 (Alarm Interrupt Enable 0) – When set to a logic 1, this bit permits the interrupt 0 request flag
(IRQF0) bit in the status register to assert
not initiate the
EOSC
SECONDS
EOSC
ALARM REGISTER MASK BITS (BIT 7)
BIT7
1
0
0
0
0
(Enable Oscillator) – This bit when set to logic 0 starts the oscillator. When this bit is set to a
MINUTES
INT0
BIT6
WP
1
1
0
0
0
signal.
HOURS
1
1
1
0
0
BIT5
0
DAYS
1
1
1
1
0
INT0
BIT4
INT0
0
Alarm once per second
Alarm when seconds match
Alarm when minutes and seconds match
Alarm hours, minutes, and seconds match
Alarm day, hours, minutes and seconds match
. When the AIE0 bit is set to logic 0, the IRQF0 bit does
pin (provided that the alarms are enabled).
7 of 22
INT0
BAT
BIT3
pin (provided that the alarm is enabled) and a
or V
0
CC2
FUNCTION
. On initial application of power, this bit
INTCN
BIT2
INT1
BIT1
AIE1
pin (provided that
INT1
AIEO
BIT0
has no