DS1388Z-3+ Maxim Integrated Products, DS1388Z-3+ Datasheet - Page 17

• Manufacturer Part Number: DS1388Z-3+
• Description: IC RTC I2C W/CHARGER 8-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/Supervisor/EEPROMr

Specifications of DS1388Z-3+

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS:hh (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Since the DS1388 does not acknowledge during an
EEPROM write cycle, acknowledge polling can be used
to determine when the cycle is complete (this feature
can be used to maximize bus throughput). Once the
master issues the STOP condition for a write command,
the DS1388 initiates the internally timed write cycle.
ACK polling can be initiated immediately. This involves
the master sending a START condition, followed by the
slave address byte for a write command (R/W = 0) to
the EEPROM. If the device is still busy with the write
cycle, then a NACK is returned. If the cycle is com-
plete, then the device returns the ACK and the master
can then proceed with the next read or write command.
The RTC registers in block 0 are accessible during an
EEPROM write cycle.
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to 1. There are three basic types of
read operations: current address read, random read,
and sequential read.
The DS1388 contains an address pointer that main-
tains the last address accessed, internally increment-
ed by 1. Therefore, if the previous access (either a
read or write operation) was to address n, the next cur-
rent address read operation would access data from
address n + 1. Upon receipt of the slave address with
the R/W bit set to 1, the DS1388 issues an acknowl-
edge and transmits the 8-bit data byte. The master
issues a NACK followed by a STOP condition, and the
DS1388 discontinues transmission.
Figure 7. Data Write—Slave Receiver Mode
S - START
A - ACKNOWLEDGE (ACK)
P - STOP
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
S
ADDRESS>
1101000
<SLAVE
I
2
Acknowledge Polling
C RTC/Supervisor with Trickle Charger
0
<R/W>
Current Address Read
A
<WORD ADDRESS (n)>
Read Operation
XXXXXXXX
SLAVE TO MASTER
____________________________________________________________________
A
XXXXXXXX
<DATA (n)>
MASTER TO SLAVE
and 512 Bytes EEPROM
Random read operations allow the master to access any
memory location in a random manner. To perform this
type of read operation, first the word address must be
set. This is done by sending the word address to the
DS1388 as part of a write operation. After the word
address is sent, the master generates a START condi-
tion following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the slave address byte
again but with the R/W bit set to 1. The DS1388 then
issues an acknowledge and transmits the 8-bit data
byte. The master issues a NACK followed by a STOP
condition, and the DS1388 discontinues transmission.
Sequential reads are initiated in the same way as a ran-
dom read except that after the DS1388 transmits the
first data byte, the master issues an acknowledge as
opposed to a STOP condition in a random read. This
directs the DS1388 to transmit the next sequentially
addressed 8-bit byte. To provide sequential reads, the
DS1388 contains an internal address pointer, which is
incremented by one at the completion of each opera-
tion. This allows the entire memory contents of the
block specified in the slave address to be serially read
during one operation. The master terminates the read
by generating a NACK followed by a STOP condition.
No page boundaries exist for read operations. When
the address pointer reaches the end of an EEPROM
block (FFh), the address pointer wraps to the beginning
(00h) of the same block.
The DS1388 can operate in the two modes illustrated in
Figures 7 and 8.
A
(X + 1 BYTES + ACKNOWLEDGE)
<DATA (n + 1)>
XXXXXXXX
DATA TRANSFERRED
A
...
<DATA (n + X)
XXXXXXXX
Sequential Read
Random Read
A
P
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