ISL12026IBZ Intersil, ISL12026IBZ Datasheet - Page 16

• Manufacturer Part Number: ISL12026IBZ
• Description: IC RTC/CALENDAR EEPROM 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/EEPROMr

Specifications of ISL12026IBZ

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Clock Format: HH
• Clock Ic Type: RTC
• Interface Type: I2C, Serial
• Memory Configuration: 512 X 8
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Write Operations
Byte Write
For a write operation, the device requires the Slave Address
Byte and the Word Address Bytes. This gives the master
access to any one of the words in the array or CCR. (Note:
Prior to writing to the CCR, the master must write a 02h, then
06h to the status register in two preceding operations to
enable the write operation. See “Writing to the Clock/Control
Registers.”) Upon receipt of each address byte, the
ISL12026 responds with an acknowledge. After receiving
both address bytes the ISL12026 awaits the eight bits of
data. After receiving the 8 data bits, the ISL12026 again
responds with an acknowledge. The master then terminates
the transfer by generating a stop condition. The ISL12026
then begins an internal write cycle of the data to the non-
volatile memory. During the internal write cycle, the device
inputs are disabled, so the device will not respond to any
requests from the master. The SDA output is at high
impedance (See Figure 16).
ARRAY
CCR
SIGNALS FROM
THE MASTER
SDA BUS
SIGNALS FROM
THE SLAVE
FIGURE 15. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES
A7
1
1
D7
0
DEVICE IDENTIFIER
16
A6
0
1
D6
0
A5
D5
1
0
0
S
A
R
T
T
1
ADDRESS
FIGURE 16. BYTE WRITE SEQUENCE
A4
D4
0
1
SLAVE
0
1
1
A3
1
D3
1
0
0
ISL12026
A
C
K
0 0 0 0 0 0 0
ADDRESS 1
WORD
A2
D2
1
0
A write to a protected block of memory is ignored, but will still
receive an acknowledge. At the end of the write command,
the ISL12026 will not initiate an internal write cycle, and will
continue to ACK commands.
Byte writes to all of the nonvolatile registers are allowed,
except the DWAn registers which require multiple byte writes
or page writes to trigger nonvolatile writes. See the Device
Operation section for more information.
Page Write
The ISL12026 has a page write operation. It is initiated in the
same manner as the byte write operation; but instead of
terminating the write cycle after the first data byte is
transferred, the master can transmit up to 15 more bytes to
the memory array and up to 7 more bytes to the clock/control
registers. The RTC registers require a page write (8 bytes),
individual register writes are not allowed. (Note: Prior to
writing to the CCR, the master must write a 02h, then 06h to
the status register in two preceding operations to enable the
write operation. See “Writing to the Clock/Control
Registers.”)
A1
D1
1
0
A
C
K
ADDRESS 0
WORD
R/W
A8
A0
D0
A
C
K
(16
SLAVE ADDRESS BYTE
BYTE PAGES)
WORD ADDRESS 1
WORD ADDRESS 0
DATA
DATA BYTE
BYTE 0
BYTE 3
BYTE 1
BYTE 2
A
C
K
O
S
T
P
October 23, 2006
FN8231.5