ISL12032IVZ-T Intersil, ISL12032IVZ-T Datasheet - Page 6

• Manufacturer Part Number: ISL12032IVZ-T
• Description: IC RTC LP BATT BACK SRAM 14TSSOP
• Manufacturer: Intersil
• Type: Clock/Calendar/NVSRAMr

Specifications of ISL12032IVZ-T

• Memory Size: 1K (128 x 8)
• Time Format: HH:MM:SS:hh (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12032IVZ-TTR

I
2
NOTES:
10. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
C Interface Specifications
2. IRQ and F
3. V
4. Specified at T
5. F
6. In order to ensure proper timekeeping, the V
7. Parameter is not 100% tested.
8. V
9. These are I
SYMBOL
t
t
t
t
t
t
HD:DAT
SU:STO
HD:STO
SU:STA
HD:STA
SU:DAT
SCL
DD
DD
t
HIGH
R
t
Cb
DH
t
t
PU
R
F
> VBAT +V
= 0V. I
= 400kHz.
OUT
BAT
2
C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification.
A
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
Input Data Setup Time
Input Data Hold Time
STOP Condition Setup Time
STOP Condition Hold Time
Output Data Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive loading of SDA or SCL
SDA and SCL Bus Pull-up Resistor
Off-chip
Inactive.
=+25°C.
increases at V
BATHYS
PARAMETER
6
DD
Specifications apply for: V
voltages between 0.5V and 1.5V.
(Continued)
DD SR-
Measured at the 70% of V
crossing.
SCL rising edge to SDA
falling edge. Both crossing
70% of V
From SDA falling edge
crossing 30% of V
falling edge crossing 70% of
V
From SDA exiting the 30% to
70% of V
rising edge crossing 30% of
V
From SCL falling edge
crossing 30% of V
entering the 30% to 70% of
V
From SCL rising edge
crossing 70% of V
rising edge crossing 30% of
V
From SDA rising edge to
SCL falling edge. Both
crossing 70% of V
From SCL falling edge
crossing 30% of V
SDA enters the 30% to 70%
of V
From 30% to 70% of V
From 70% to 30% of V
Total on-chip and off-chip
Maximum is determined by
t
For Cb = 400pF, max is about
2kΩ.
For Cb = 40pF, max is about
15kΩ
specification must be followed.
R
DD
DD.
DD
DD
and t
DD
TEST CONDITIONS
.
.
window.
window.
F
DD
.
ISL12032
DD
DD
= 2.7V to 5.5V, T
.
window, to SCL
DD
DD
DD
DD
DD
, to SDA
.
, until
to SDA
to SCL
DD.
DD.
DD
A
= -40°C to +85°C, unless otherwise stated.
20 + 0.1 x Cb
20 + 0.1 x Cb
(Note 10)
MIN
600
600
600
100
600
600
10
0
0
1
(Note 4)
TYP
(Note 10) UNITS
MAX
900
300
300
400
kΩ
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
ns
April 16, 2009
NOTES
7, 9
7, 9
7, 9
7, 9
FN6618.2