ISL12027IB27Z-T Intersil, ISL12027IB27Z-T Datasheet - Page 19

• Manufacturer Part Number: ISL12027IB27Z-T
• Description: IC RTC/CALENDAR EEPROM 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/Supervisor/EEPROMr

Specifications of ISL12027IB27Z-T

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Bus Type: Serial (I2C)
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 8
• Mounting: Surface Mount
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12027IB27Z-TTR

Device Addressing
Following a start condition, the master must output a Slave
Address Byte. The first 4 bits of the Slave Address Byte
specify access to either the EEPROM array or to the CCR.
Slave bits ‘1010’ access the EEPROM array. Slave bits
‘1101’ access the CCR.
When shipped from the factory, EEPROM array is
UNDEFINED, and should be programmed by the customer
to a known state.
Bit 3 through Bit 1 of the slave byte specify the device select
bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the operation
to be performed. When this R/W bit is a one, then a read
operation is selected. A zero selects a write operation. Refer
to Figure 19.
After loading the entire Slave Address Byte from the SDA
bus, the ISL12027 compares the device identifier and device
select bits with ‘1010111’ or ‘1101111’. Upon a correct
compare, the device outputs an acknowledge on the SDA
line.
Following the Slave Byte is a 2 byte word address. The word
address is either supplied by the master device or obtained
from an internal counter. On power-up the internal address
counter is set to address 0h, so a current address read of the
EEPROM array starts at address 0. When required, as part
of a random read, the master must supply the 2 Word
Address Bytes as shown in Figure 19.
In a random read operation, the slave byte in the “dummy
write” portion must match the slave byte in the “read”
section. That is if the random read is from the array the slave
byte must be 1010111x in both instances. Similarly, for a
random read of the Clock/Control Registers, the slave byte
must be 1101111x in both places.
Write Operations
Byte Write
For a write operation, the device requires the Slave Address
Byte and the Word Address Bytes. This gives the master
access to any one of the words in the array or CCR. (Note:
Prior to writing to the CCR, the master must write a 02h, then
06h to the status register in two preceding operations to
enable the write operation. See “Writing to the Clock/Control
Registers”). Upon receipt of each address byte, the
ISL12027 responds with an acknowledge. After receiving
both address bytes the ISL12027 awaits the 8-bits of data.
After receiving the 8-data bits, the ISL12027 again responds
with an acknowledge. The master then terminates the
transfer by generating a stop condition. The ISL12027 then
begins an internal write cycle of the data to the non-volatile
memory. During the internal write cycle, the device inputs
are disabled, so the device will not respond to any requests
19
ISL12027, ISL12027A
from the master. The SDA output is at high impedance (see
Figure 20).
A write to a protected block of memory is ignored, but will still
receive an acknowledge. At the end of the write command,
the ISL12027 will not initiate an internal write cycle, and will
continue to ACK commands.
Byte writes to all of the non-volatile registers are allowed,
except the DWAn registers which require multiple byte writes
or page writes to trigger non-volatile writes. See “Device
Operation” on page 14 for more information.
Page Write
The ISL12027 has a page write operation. It is initiated in the
same manner as the byte write operation; but instead of
terminating the write cycle after the first data byte is
transferred, the master can transmit up to 15 more bytes to
the memory array and up to 7 more bytes to the clock/control
registers. The RTC registers require a page write (8 bytes),
individual register writes are not allowed. (Note: Prior to
writing to the CCR, the master must write a 02h, then 06h to
the status register in two preceding operations to enable the
write operation. See “Writing to the Clock/Control Registers”
on page 14”)
After the receipt of each byte, the ISL12027 responds with
an acknowledge, and the address is internally incremented
by one. The address pointer remains at the last address byte
written. When the counter reaches the end of the page, it
“rolls over” and goes back to the first address on the same
page. This means that the master can write 16 bytes to a
memory array page or 8 bytes to a CCR section starting at
any location on that page. For example, if the master begins
writing at location 10 of the memory and loads 15 bytes, then
the first 6 bytes are written to addresses 10 through 15, and
the last 6 bytes are written to columns 0 through 5.
Afterwards, the address counter would point to location 6 on
the page that was just written. If the master supplies more
than the maximum bytes in a page, then the previously
loaded data is over-written by the new data, one byte at a
time. Refer to Figure 21.The master terminates the Data
Byte loading by issuing a stop condition, which causes the
ISL12027 to begin the non-volatile write cycle. As with the
byte write operation, all inputs are disabled until completion
of the internal write cycle. Refer to Figure 22 for the address,
acknowledge and data transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must be sent
by the master after sending at least 1 full data byte and it’s
associated ACK signal. If a stop is issued in the middle of a
data byte, or before 1 full data byte + ACK is sent, then the
ISL12027 resets itself without performing the write. The
contents of the array are not affected.
August 12, 2010
FN8232.8