ISL1220IUZ-T Intersil, ISL1220IUZ-T Datasheet - Page 12

• Manufacturer Part Number: ISL1220IUZ-T
• Description: IC RTC LP BATT BACK SRAM 10MSOP
• Manufacturer: Intersil
• Type: Clock/Calendar/Alarmr

Specifications of ISL1220IUZ-T

• Memory Size: 8B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL1220IUZ-TTR

NOTE: Writing to register 08h has restrictions. If V
byte writes to register 08h are allowed, only page writes beginning
with register 07h. If V
allowed, as well as page writes.
FREQUENCY OUT CONTROL BITS (FO <3:0>)
These bits enable/disable the frequency output function and
select the output frequency at the F
frequency selection. If all bits are set to Zero, the F
function is disabled.
FREQUENCY OUTPUT BIT (FOBATB)
This bit enables/disables the F
mode (i.e. V
set to “1” the F
mode. This means the frequency output function is disabled.
When the FOBATB is cleared to “0”, the F
during battery backup mode. The F
output and requires a pull up resistor to V
battery backup mode
LOW POWER MODE BIT (LPMODE)
This bit enables/disables low power mode. With
LPMODE = “0”, the device will be in normal mode and the
V
V
power mode and the V
V
about 600nA when using LPMODE = “1” with V
FREQUENCY,
BAT
DD
DD
32768
F
< V
< V
4096
1024
1/16
1/32
supply will be used when V
1/2
1/4
1/8
OUT
64
32
16
TABLE 4. FREQUENCY SELECTION OF F
0
8
4
2
1
TRIP
BAT
BAT
. With LPMODE = “1”, the device will be in low
- V
OUT
UNITS
BATHYS
power source active). When the FOBATB is
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
DD
pin is disabled during battery backup
>V
BAT
BAT
. There is a supply current saving of
FO3
, then a byte write to register 08h IS
supply will be used when
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
12
OUT
DD
pin during battery backup
OUT
OUT
FO2
< V
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
pin is open drain
BAT
pin. See Table 4 for
BAT
OUT
BAT
- V
for operation in
FO1
pin is enabled
OUT
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
>V
DD
BATHYS
DD
PIN
OUT
= 5V.
, then no
FO0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
and
ISL1220
(See Typical Performance Curves: I
LPMODE ON AND OFF.)
ALARM ENABLE BIT (ALME)
This bit enables/disables the alarm function. When the ALME
bit is set to “1”, the alarm function is enabled. When the ALME
is cleared to “0”, the alarm function is disabled. The alarm
function can operate in either a single event alarm or a periodic
interrupt alarm (see IM bit).
NOTE: When the frequency output mode is enabled, the alarm function
is disabled.
INTERRUPT/ALARM MODE BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will operate
in the interrupt mode, where an active low pulse width of
250ms will appear at the IRQ pin when the RTC is triggered
by the alarm as defined by the alarm registers (0Ch to 11h).
When the IM bit is cleared to “0”, the alarm will operate in
standard mode, where the IRQ pin will be tied low until the
ALM status bit is cleared to “0”.
Analog Trimming Register
ANALOG TRIMMING REGISTER (ATR<5:0>)
Six analog trimming bits, ATR0 to ATR5, are provided in
order to adjust the on-chip load capacitance value for
frequency compensation of the RTC. Each bit has a different
weight for capacitance adjustment. For example, using a
Citizen CFS-206 crystal with different ATR bit combinations
provides an estimated ppm adjustment range from -34 to
+80ppm to the nominal frequency compensation. The
combination of analog and digital trimming can give up to -94
to +140ppm of total adjustment.
The effective on-chip series load capacitance, C
ranges from 4.5pF to 20.25pF with a mid-scale value of
IM BIT
0
1
X1
X2
FIGURE 11. DIAGRAM OF ATR
Single Time Event Set By Alarm
Repetitive/Recurring Time Event Set By Alarm
C
C
X1
X2
INTERRUPT/ALARM FREQUENCY
OSCILLATOR
DD
CRYSTAL
vs V
CC
with
LOAD
June 22, 2006
,
FN6315.0