M48T58-70PC1 STMicroelectronics, M48T58-70PC1 Datasheet - Page 8

• Manufacturer Part Number: M48T58-70PC1
• Description: IC TIMEKPR NVRAM 64KBIT 5V 28-DI
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T58-70PC1

• Memory Size: 64K (8K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.75 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 28-DIP Module (600 mil), 28-EDIP
• Function: Clock/Calendar/NV Timekeeping RAM/Battery Backup
• Rtc Memory Size: 8192 Byte
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.75 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Rtc Bus Interface: Parallel
• Clock Format: HH
• Clock Ic Type: Timekeeper
• Memory Configuration: 8K X 8
• Supply Voltage Range: 4.75V To 5.5V
• Digital Ic Case Style: DIP
• No. Of Pins: 28
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2857-5

Operation modes
2
Note:
8/33
Operation modes
As
oscillator of the M48T58/Y are integrated on one silicon chip. The two circuits are
interconnected at the upper eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh. The clock
locations contain the century, year, month, date, day, hour, minute, and second in 24 hour
BCD format (except for the century). Corrections for 28, 29 (leap year - valid until 2100), 30,
and 31 day months are made automatically. Byte 1FF8h is the clock control register. This
byte controls user access to the clock information and also stores the clock calibration
setting.
The eight clock bytes are not the actual clock counters themselves; they are memory
locations consisting of BiPORT™ READ/write memory cells. The M48T58/Y includes a
clock control circuit which updates the clock bytes with current information once per second.
The information can be accessed by the user in the same manner as any other location in
the static memory array.
The M48T58/Y also has its own power-fail detect circuit. The control circuitry constantly
monitors the single 5 V supply for an out-of-tolerance condition. When V
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V
battery backup switchover voltage (V
maintains data and clock operation until valid power returns.
Table 2.
1. See
X = V
Deselect
Deselect
WRITE
READ
READ
Deselect
Deselect
Mode
Figure 4 on page 7
IH
Table 11 on page 24
or V
IL
4.75 to 5.5 V
V
Operating modes
4.5 to 5.5 V
; V
SO
≤ V
(min)
V
SO
to V
or
SO
CC
(1)
= Battery backup switchover voltage.
(1)
PFD
shows, the static memory array and the quartz controlled clock
for details.
V
V
V
V
E1
X
X
X
IH
IL
IL
IL
Doc ID 2412 Rev 7
V
V
V
V
E2
SO
X
X
X
IH
IH
IH
IL
), the control circuitry connects the battery which
V
V
G
X
X
X
X
X
IH
IL
V
V
V
W
X
X
X
X
IH
IH
IL
DQ0-DQ7
High Z
High Z
High Z
High Z
High Z
CC
D
D
OUT
. As V
IN
CC
Battery backup mode
CC
M48T58, M48T58Y
falls below the
CMOS standby
is out of
Standby
Standby
Power
Active
Active
Active