M41T82RM6F STMicroelectronics, M41T82RM6F Datasheet - Page 20

• Manufacturer Part Number: M41T82RM6F
• Description: IC RTC SERIAL W/BATT SW 8-SOIC
• Manufacturer: STMicroelectronics
• Type: Clock/Calendar/Alarmr

Specifications of M41T82RM6F

• Memory Size: 32B
• Time Format: HH:MM:SS:hh (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8279-2; M41T82RM6F

Clock operation
3.1
Note:
3.2
20/61
Power-down time-stamp
When a power failure occurs, the time/date counters are copied into the buffer/transfer
registers and the halt update bit (HT) is automatically set to a "1". The HT bit prevents the
normal copying from counters to registers which occurs at the start of a read or write cycle.
Thus, upon power-up, the user can read the RTC registers to ascertain the time of power-
down. Additional reads will return the same time. It will appear to be frozen until the HT bit
(D6, address 0Ch) is written to 0 by the user. Then, subsequent reads will then return the
current time. For more information, see application notes AN1572 and AN3060.
Writes to the RTC registers (addresses 00h to 07h) with the HT bit set can cause time
corruption. Example: Assume a power-fail time of Monday, November 16, 2009, at
17:52:27.03. At the next power-up, that time will be frozen in the buffer/transfer registers.
On November 17, 2009, at 16:15:07.77, the user powers the system back up and tries to
write the seconds to 35 while the HT bit is still set. This will cause Monday, November 16,
2009, at 17:52:35.03 to be written into the counters because the other seven bytes of
buffer/transfer register still contain the time of power-down. The result is that the modified
time of power-down was written into the counters making it appear the part had lost time
while power was off. Thus, at power-up, the user should always clear the HT bit (write D6 to
0 in address 0Ch) before writing to any address in the range 00h to 07h.
A typical power-up flow is to read the time of power-down, then clear the HT bit, then read
the current time. If the time of power-down is not needed by the application, then the first
step can be omitted.
Clock/control register map and divider chain
The M41T8x is comprised of 32 addresses which contain registers for clock (time and date),
calibration (digital and analog), alarm 1 and 2, watchdog, flags, timer, and square wave
(M41T83 only). Clock and alarm registers store data in BCD format. Calibration, timer,
watchdog, and square wave bits are written in a binary format.
Whenever any of the eight RTC bytes (addresses 00h to 07h) are written, the internal divider
(or clock) chain will be reset upon the completion of the write cycle.
Doc ID 12578 Rev 12
M41T82-M41T83