PCF8563T/F4,112 NXP Semiconductors, PCF8563T/F4,112 Datasheet - Page 22

• Manufacturer Part Number: PCF8563T/F4,112
• Description: IC REAL TIME CLK/CALENDAR 8-SOIC
• Manufacturer: NXP Semiconductors
• Type: Clock/Calendarr

Specifications of PCF8563T/F4,112

• Package / Case: 8-SOIC (3.9mm Width)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Function: Clock/Calendar/Alarm/Timer Interrupt
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Serial (2-Wire, I2C)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-3615 - DEMO BOARD I2C
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-5029; 935262217112; PCF8563T/F4,112; PCF8563TD; PCF8563TD

NXP Semiconductors
PCF8563
Product data sheet
Fig 16. System configuration
SDA
SCL
TRANSMITTER
9.4 Acknowledge
RECEIVER
MASTER
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
Acknowledgement on the I
Fig 17. Acknowledgement on the I
•
•
•
•
A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
by transmitter
data output
by receiver
data output
SCL from
master
RECEIVER
SLAVE
All information provided in this document is subject to legal disclaimers.
condition
START
Rev. 8 — 18 November 2010
S
2
C-bus is illustrated in
TRANSMITTER
RECEIVER
SLAVE
1
2
C-bus
2
TRANSMITTER
Figure
MASTER
17.
not acknowledge
acknowledge
Real-time clock/calendar
8
TRANSMITTER
RECEIVER
MASTER
acknowledgement
clock pulse for
PCF8563
© NXP B.V. 2010. All rights reserved.
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