PCF8563T/F4,112 NXP Semiconductors, PCF8563T/F4,112 Datasheet - Page 21

• Manufacturer Part Number: PCF8563T/F4,112
• Description: IC REAL TIME CLK/CALENDAR 8-SOIC
• Manufacturer: NXP Semiconductors
• Type: Clock/Calendarr

Specifications of PCF8563T/F4,112

• Package / Case: 8-SOIC (3.9mm Width)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Function: Clock/Calendar/Alarm/Timer Interrupt
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Serial (2-Wire, I2C)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-3615 - DEMO BOARD I2C
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-5029; 935262217112; PCF8563T/F4,112; PCF8563TD; PCF8563TD

NXP Semiconductors
9. Characteristics of the I
PCF8563
Product data sheet
9.1 Bit transfer
9.2 START and STOP conditions
9.3 System configuration
The I
The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START
condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P (see
A device generating a message is a transmitter; a device receiving a message is a
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves (see
Fig 14. Bit transfer
Fig 15. Definition of START and STOP conditions
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
SDA
SCL
START condition
All information provided in this document is subject to legal disclaimers.
2
SDA
SCL
Figure
C-bus
S
Rev. 8 — 18 November 2010
15).
data valid
data line
stable;
Figure
Figure
allowed
change
of data
14).
16).
STOP condition
Real-time clock/calendar
mbc621
P
PCF8563
© NXP B.V. 2010. All rights reserved.
mbc622
SDA
SCL
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