PCA8565TS/1,118 NXP Semiconductors, PCA8565TS/1,118 Datasheet - Page 22

• Manufacturer Part Number: PCA8565TS/1,118
• Description: IC CMOS RTC/CALENDAR 8-TSSOP
• Manufacturer: NXP Semiconductors
• Type: Clock/Calendarr

Specifications of PCA8565TS/1,118

• Package / Case: 8-TSSOP
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1902-2; 935272132118; PCA8565TS-T

NXP Semiconductors
PCA8565_2
Product data sheet
Fig 15. System configuration
SCL
SDA
10.4 Acknowledge
TRANSMITTER /
RECEIVER
MASTER
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
bit. The acknowledge bit is a HIGH-level signal put on the bus by the transmitter during
which time the master generates an extra acknowledge related clock pulse. A slave
receiver which is addressed must generate an acknowledge after the reception of each
byte. Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge
related clock pulse (set-up and hold times must be taken into consideration). A master
receiver must signal an end of data to the transmitter by not generating an acknowledge
on the last byte that has been clocked out of the slave. In this event the transmitter must
leave the data line HIGH to enable the master to generate a STOP condition.
Fig 16. Acknowledgement on the I
by transmitter
data output
by receiver
data output
SCL from
master
RECEIVER
SLAVE
condition
START
S
Rev. 02 — 16 June 2009
TRANSMITTER /
RECEIVER
SLAVE
1
2
C-bus
2
TRANSMITTER
MASTER
not acknowledge
acknowledge
Real time clock/calendar
8
TRANSMITTER /
RECEIVER
MASTER
acknowledgement
clock pulse for
PCA8565
© NXP B.V. 2009. All rights reserved.
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