LTC6991IS6#TRPBF Linear Technology, LTC6991IS6#TRPBF Datasheet - Page 18

• Manufacturer Part Number: LTC6991IS6#TRPBF
• Description: IC TIMERBLOX OSCILLATOR TSOT23-6
• Manufacturer: Linear Technology

Specifications of LTC6991IS6#TRPBF

• Frequency: *
• Voltage - Supply: *
• Current - Supply: 135µA
• Operating Temperature: *
• Package / Case: TSOT-23-6, TSOT-6
• Count: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LTC6991
applicaTions inForMaTion
1. Connect the bypass capacitor, C1, directly to the V
2. Place all passive components on the top side of the

GND pins using a low inductance path. The connection
from C1 to the V
layer. For the DFN package, C1’s connection to GND is
also simply done on the top layer. For the TSOT-23, OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that, C1’s GND connection can be accomplished through
multiple vias to the ground plane. Multiple vias for both
the GND pin connection to the ground plane and the
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1µF ceramic capacitor.
board. This minimizes trace inductance.
+
pin is easily done directly on the top
R2
R1
SET
DIV
V
V
+
+
R
C1
SET
DFN PACKAGE
Figure 18. Supply Bypassing and PCB Layout
GND
OUT
RST
R
SET
+
and
RST
GND
SET
LTC6991
3. Place R
4. Connect R
5. Use a ground trace to shield the SET pin. This provides
6. Place R1 and R2 close to the DIV pin. A direct, short
OUT
DIV
V
+
make a direct, short connection. The SET pin is a
current summing node and currents injected into this
pin directly modulate the operating frequency. Having
a short connection minimizes the exposure to signal
pickup.
or vias to the ground plane will not have a significant
affect on accuracy, but a direct, short connection is
recommended and easy to apply.
another layer of protection from radiated signals.
connection to the DIV pin minimizes the external signal
coupling.
C1
0.1µF
SET
GND
R
RST
SET
SET
SET
TSOT-23 PACKAGE
as close as possible to the SET pin and
R1
R2
directly to the GND pin. Using a long path
V
+
R2
OUT
DIV
C1
V
+
6991 F18
R1
V
+
6991f