CY28411OXC-1 Cypress Semiconductor Corp, CY28411OXC-1 Datasheet

IC CLOCK GEN ALVISO 56-SSOP

CY28411OXC-1

Manufacturer Part Number
CY28411OXC-1
Description
IC CLOCK GEN ALVISO 56-SSOP
Manufacturer
Cypress Semiconductor Corp
Type
Fanout Distribution, Spread Spectrum Clock Generatorr
Datasheet

Specifications of CY28411OXC-1

Pll
Yes
Input
LVTTL, Crystal
Output
Clock
Number Of Circuits
1
Ratio - Input:output
7:20
Differential - Input:output
No/Yes
Frequency - Max
266MHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
56-SSOP
Frequency-max
100MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Cypress Semiconductor Corporation
Document #: 38-07694 Rev. *B
Features
CPU_STP#
VTT_PWRGD#
• Compliant to Intel
• Supports Intel Pentium-M CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100-MHz differential SRC clocks
• 96-MHz differential dot clock
• 48-MHz USB clocks
Block Diagram
PCI_STP#
FS_[C:A]
SDATA
XOUT
SCLK
IREF
XIN
PD
PLL1
PLL2
Logic
XTAL
OSC
I
2
C
Network
Divider
CK410M
PLL Ref Freq
Clock Generator for Intel
3901 North First Street
DOT96T
DOT96C
VDD_REF
REF
VDD_CPU
VDD_SRC
VDD_PCI
VDD_PCIF
VDD_48 MHz
USB_48
CPUT[0:1], CPUC[0:1],
CPU(T/C)2_ITP]
SRCT[0:6], SRCC[0:6]
PCI[2:5]
PCIF[0:1]
FS_B/TEST_MODE
VTT_PWRGD#/PD
• 33-MHz PCI clock
• Low-voltage frequency select input
• I
• Ideal Lexmark Spread Spectrum profile for maximum
• 3.3V power supply
• 56-pin SSOP and TSSOP packages
x2 / x3
PCIF0/ITP_EN
USB_48/FS_A
SRC4_SATAC
CPU
SRC4_SATAT
electromagnetic interference (EMI) reduction
2
C support with readback capabilities
VDD_SRC
VDD_SRC
VDD_PCI
VDD_PCI
VSS_PCI
VSS_PCI
Pin Configuration
DOT96C
DOT96T
VDD_48
VSS_48
SRCC0
SRCC1
SRCC2
SRCC3
SRCT0
SRCT1
SRCT2
SRCT3
PCIF1
PCI3
PCI4
PCI5
x7 / x8
SRC
San Jose
56 SSOP/TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PCI
x 6
,
CA 95134
Revised March 10, 2005
Alviso Chipset
REF
x 1
32
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
31
30
29
DOT96 USB_48
PCI2
PCI_STP#
CPU_STP#
FS_C/TEST_SEL
REF
VSS_REF
XIN
XOUT
VDD_REF
SDATA
SCLK
VSS_CPU
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
IREF
VSSA
VDDA
CPUT2_ITP/SRCT7
CPUC2_ITP/SRCC7
VDD_SRC
SRCT6
SRCC6
SRCT5
SRCC5
VSS_SRC
CY28411-1
x 1
408-943-2600
x 1

Related parts for CY28411OXC-1

CY28411OXC-1 Summary of contents

Page 1

... IREF PD PLL2 2 SDATA I C SCLK Logic Cypress Semiconductor Corporation Document #: 38-07694 Rev. *B Clock Generator for Intel • 33-MHz PCI clock • Low-voltage frequency select input 2 • support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • ...

Page 2

Pin Definitions Pin No. Name 54 CPU_STP# 44,43,41,40 CPUT/C 36,35 CPUT2_ITP/SRCT7, CPUC2_ITP/SRCC7 14,15 DOT96T, DOT96C 12 FS_A/USB_48 16 FS_B/TEST_MODE 53 FS_C/TEST_SEL 39 IREF 56,3,4,5 PCI 55 PCI_STP# 8 PCIF0/ITP_EN 9 PCIF1 52 REF 46 SCLK 47 SDATA 26,27 SRC4_SATAT, SRC4_SATAC ...

Page 3

Frequency Select Pins (FS_A, FS_B and FS_C) Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled low by ...

Page 4

Table 3. Block Read and Block Write Protocol (continued) Block Write Protocol Bit Description 28 Acknowledge from slave 36:29 Data byte 1 – 8 bits 37 Acknowledge from slave 45:38 Data byte 2 – 8 bits 46 Acknowledge from slave ...

Page 5

Byte 0:Control Register 0 (continued) Bit @Pup 2 1 SRC[T/C SRC[T/C SRC[T/C]0 Byte 1: Control Register 1 Bit @Pup DOT_96T USB_48 Reserved 2 1 CPU[T/C]1 1 ...

Page 6

Byte 3: Control Register 3 (continued) Bit @Pup Byte 4: Control Register 4 Bit @Pup 7 0 Reserved 6 0 DOT96T Reserved ...

Page 7

Byte 6: Control Register 6 Bit @Pup Reserved PCIF, SRC, PCI 2 Externally CPUT/C selected 1 Externally CPUT/C selected 0 Externally CPUT/C selected Byte 7: Vendor ID Bit @Pup 7 ...

Page 8

Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with ...

Page 9

PD (Power-down) Clarification The VTT_PWRGD# /PD pin is a dual function pin. During initial power-up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled low by the clock chip, the pin assumes PD functionality. The PD pin is an ...

Page 10

CPU_STP# Assertion The CPU_STP# signal is an active low input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. When the CPU_STP# pin is asserted, all CPU outputs that ...

Page 11

CPU_STOP# PD CPUT(Free Running) CPUC(Free Running) CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C Figure 8. CPU_STP# = Hi-Z, CPU_PD = Hi-Z, DOT_PD = tHi-Z [1] PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI ...

Page 12

FS_A, FS_B,FS_C VTT_PW RGD# PW RGD_VRM VDD Clock Gen Clock State State 0 Off Clock Outputs Off Clock VCO VDD_A = 2.0V S0 Power Off Figure 12. Clock Generator Power-up/Run State Diagram Document #: 38-07694 Rev. *B 0.2-0.3mS W ait ...

Page 13

Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DD_A V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J Ø Dissipation, Junction to Case JC (Mil-Spec 883E ...

Page 14

AC Electrical Specifications Parameter Description Crystal T XIN Duty Cycle DC T XIN Period PERIOD XIN Rise and Fall Times XIN Cycle to Cycle Jitter CCJ L Long-term Accuracy ACC CPU at 0.7V T ...

Page 15

AC Electrical Specifications Parameter Description T SRCT/C Cycle to Cycle Jitter CCJ L SRCT/C Long Term Accuracy ACC SRCT and SRCC Rise and Fall Times Rise/Fall Matching RFM ∆T Rise TimeVariation R ∆T Fall ...

Page 16

AC Electrical Specifications Parameter Description T Period PERIOD T Absolute Period PERIODAbs T USB high time HIGH T USB low time LOW Rise and Fall Times Cycle to Cycle Jitter CCJ REF T REF ...

Page 17

... Ω Figure 15. Single-ended Output Signals (for AC Parameters Measurement) Ordering Information Part Number Lead-free CY28411OXC-1 56-pin SSOP CY28411OXCT-1 56-pin SSOP – Tape and Reel CY28411ZXC-1 56-pin TSSOP CY28411ZXCT-1 56-pin TSSOP – Tape and Reel Document #: 38-07694 Rev Ω Ω Ω D iff tia Ω ...

Page 18

... Document #: 38-07694 Rev. *B © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

Page 19

Document History Page Document Title: CY28411-1 Clock Generator for Intel Document Number: 38-07694 REV. ECN NO. Issue Date ** 246811 See ECN *A 299753 See ECN *B 331934 See ECN Document #: 38-07694 Rev. *B  Alviso Chipset Orig. of ...

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