CY28409 Cypress Semiconductor, CY28409 Datasheet
CY28409
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CY28409 Summary of contents
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... PCI3 2 PCI[0:6] VDD_PCI VSS_PCI PCI4 3V66_4/VCH PCI5 PCI6 VDD_48MHz PD# DOT_48 3V66_0 USB_48 3V66_1 VDD_3V66 VSS_3V66 3V66_2 3V66_3 SCLK • 3901 North First Street • CY28409 3V66 PCI REF [ FS_B 2 55 VDD_A 3 54 VSS_A 4 53 VSS_IREF 5 52 ...
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... LVTTL input is a level sensitive strobe used to latch the FS_A and FS_B inputs (active low). SMBus-compatible SDATA. SMBus-compatible SCLOCK. Ground for current reference. Ground for PLL. Ground for outputs. Ground for outputs. Ground for outputs. Ground for outputs. Ground for outputs. Ground for outputs. CY28409 Description Page ...
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... The block write and block read protocol is outlined in Table 4 while Table 5 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Description Bit 1 2 11:18 19 CY28409 has been sampled low, REF0 REF1 14.3 MHz 14.31 MHz REF/N REF/N 14 ...
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... Reserved, Set = 0 PCI Drive Strength Override 0 = Force All PCI and PCIF Outputs to Low Drive Strength 1 = Force All PCI and PCIF Outputs to High Drive Strength Reserved, Set = 0 Reserved, Set = 0 CY28409 Block Read Protocol Description Repeat start Slave address – 7 bits Read = 1 Acknowledge from slave Byte count from slave – ...
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... When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI,PCIF and SRC outputs will resume in a synchronous manner with no short pulses. PCI6 Output Enable 0 = Disabled Enabled CY28409 Description Description Description Description Page ...
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... Reserved, Set = 1 VCH Select 66 MHz/48 MHz 0 = 3V66 mode VCH (48 MHz) mode 3V66_4/VCH Output Enable 0 = Disabled Enabled 3V66_3 Output Enable 0 = Disabled Enabled 3V66_2 Output Enable 0 = Disabled Enabled 3V66_1 Output Enable 0 = Disabled Enabled 3V66_0 Output Enable 0 = Disabled Enabled CY28409 Description Description Description Page ...
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... Crystal Recommendations The CY28409 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28409 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. ...
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... P in the LOW state may require more than one clock cycle complete CY28409 Load Capacitance (each side – (Cs + Ci) Total Capacitance (as seen by the crystal ...
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... PD# CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF Figure 4. Power-down Deassertion Timing Waveform Document #: 38-07445 Rev. *B Figure 3. Power-down Assertion Timing Waveform Tstable <1.8nS Tdrive_PWRDN# <300 S, >200mV CY28409 Page ...
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... The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles CPU_STP# CPUT CPUC CPU Internal Document #: 38-07445 Rev. *B Figure 5. CPU_STP# Assertion Waveform Tdrive_CPU_STP#,10nS>200mV Figure 6. CPU_STP# Deassertion Waveform CY28409 Page ...
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... Byte 0 Bit 3 will return a 0 value if either of these control bits are set LOW thereby indicating the device’s stoppable PCI clocks are not running. Document #: 38-07445 Rev (See SU Tsu Figure 7. PCI_STP# Assertion Waveform Tdrive_SRC Tsu Figure 8. PCI_STP# Deassertion Waveform CY28409 Page ...
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... Wait for Sample Sels Delay VTT_PWRGD# State 1 State 2 On Figure 9. VTT_PWRGD# Timing Diagram S1 VTT_PWRGD# = Low Delay >0.25mS S3 VDDA = off Normal Operation VTT_PWRGD# = toggle CY28409 Device is not affected, VTT_PWRGD# is ignored State Sample Inputs straps Wait for <1.8ms Enable Outputs Page ...
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... MIL-STD-883, Method 3015 @ 1/8 in. Condition 3.3 ± 5% SDATA, SCLK SDATA, SCLK except internal pull-ups resistors, 0 < V except internal pull-down resistors, 0 < – All outputs loaded per Table 9 and Figure 11 PD# Asserted CY28409 Min. Max. Unit –0.5 4.6 V –0.5 4.6 V –0 0.5 VDC DD –65 150 ° ...
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... Measured at crossing point V OX Measured from V = 0.175 0.525V OL OH Determined as a fraction of 2*(T – T )/( Math averages Figure 11 Math averages Figure 11 See Figure 11. Measure SE Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.0V Measurement at 0.8V CY28409 Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns – 10 – 500 ps 300 ppm 45 ...
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... Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured at crossing point V Measured between 0.8V and 2.0V Measurement at 1.5V Table 8. USB to DOT Phase Offset Offset Parameter Min. Max. DOT Skew 1.5 ns 3.5 ns USB Skew VCH SKew CY28409 Min. Max. 0.5 2.0 – 250 – 250 45 55 29.9910 30.0009 29.9910 30.1598 12.0 – ...
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... Reference R, I – V (3*R REF 475 1 2.32 mA REF REF Package Type CY28409 Output Current REF ...
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... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 56-lead Shrunk Small Outline Package O56 2 C system, provided that the system conforms to the I CY28409 51-85062-*C 51-85060-* Standard Specification ...
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... Document History Page Document Title: CY28409 Clock Synthesizer with Differential SRC and CPU Outputs Document Number: 38-07445 REV. ECN NO. Issue Date ** 121414 12/04/02 *A 124795 07/07/03 *B 128864 08/29/03 Document #: 38-07445 Rev. *B Orig. of Change RGL New Data Sheet RGL Changed revision code to 4 Corrected rise/fall time value on DOT from 1.0/2.0 to 0.5/1.0 ns, respectively Changed USB and DOT from long-term jitter to cycle-to-cycle jitter Changed USB and DOT period value from 28 ...