IDT82V3280PFG IDT, Integrated Device Technology Inc, IDT82V3280PFG Datasheet - Page 40

• Manufacturer Part Number: IDT82V3280PFG
• Description: IC PLL WAN SE STRATUM 2 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3280PFG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3280PFG

Table 24: Outputs on OUT1 ~ OUT7 if Derived from T0/T4 DPLL Outputs
Functional Description
IDT82V3280
Note:
1. 1 ≤ n ≤ 7. Each output is assigned a frequency divider.
2. E1 = 2.048 MHz, T1 = 1.544 MHz, E3 = 34.368 MHz, T3 = 44.736 MHz. The blank cell means the configuration is reserved.
OUTn_DIVIDER[3:0]
(Output Divider)
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
1100
1101
0111
1110
1111
1
77.76 MHz
64 kHz
400 Hz
8 kHz
2 kHz
1Hz
12E1
12E1
6E1
3E1
2E1
E1
16E1
16E1
8E1
4E1
2E1
E1
outputs on OUT1 ~ OUT7 if derived from T0/T4 DPLL outputs
24T1
24T1
12T1
6T1
4T1
3T1
2T1
T1
Output is disabled (output high).
Output is disabled (output low).
40
16T1
16T1
8T1
4T1
2T1
T1
E3
E3
T3
T3
(26 MHz)
13 MHz
2
GSM
(30.72 MHz)
15.36 MHz
OBSAI
December 9, 2008
WAN PLL
(40 MHz)
GPS
20
10
5