IDT82V3280PFG IDT, Integrated Device Technology Inc, IDT82V3280PFG Datasheet - Page 26

• Manufacturer Part Number: IDT82V3280PFG
• Description: IC PLL WAN SE STRATUM 2 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3280PFG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3280PFG

Table 9: Related Bit / Register in Chapter 3.6
3.6.2
T0_INPUT_SEL[3:0] / T4_INPUT_SEL[3:0] bits. The results of input
clocks quality monitoring (refer to
toring) do not affect the input clock selection.
3.6.3
validity, priority and locking allowance configuration. The validity
Functional Description
Note: * The setting in the 26 ~ 2C registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit.
IDT82V3280
In Forced selection, the selected input clock is set by the
In Automatic selection, the input clock selection is determined by its
No
FORCED SELECTION
AUTOMATIC SELECTION
INn_SEL_PRIORITY[3:0] (14 ≥ n ≥ 1)
Input Clock Quality Monitoring
(LOS, Activity, Frequency)
INn = '1', (14 > n > 1)
INn_VALID (14 ≥ n ≥ 1)
T0_INPUT_SEL[3:0]
T4_INPUT_SEL[3:0]
INn (14 ≥ n ≥ 1)
T4_LOCK_T0
Validity
T0_FOR_T4
T4_T0_SEL
EXT_SW
Yes
Bit
Chapter 3.5 Input Clock Quality Moni-
Figure 6. Qualified Input Clocks for Automatic Selection
All qualified input clocks are available for Automatic selection
No
INn_SEL_PRIORITY[3:0]
'0000', (14 > n > 1)
Priority
26
Yes
depends on the results of input clock quality monitoring (refer to
Chapter 3.5 Input Clock Quality
figured by the corresponding INn_VALID bit(14 ≥ n ≥ 1). Refer to
Figure
is
INn_SEL_PRIORITY[3:0] bits (14 ≥ n ≥ 1). If more than one qualified
input clock INn is available and has the same priority, the input clock
with the smallest ‘n’ is selected.
INPUT_VALID1_STS, INPUT_VALID2_STS
selected.
IN13_IN14_SEL_PRIORITY_CNFG
IN1_IN2_SEL_PRIORITY_CNFG ~
REMOTE_INPUT_VALID1_CNFG,
REMOTE_INPUT_VALID2_CNFG
6. In all the qualified input clocks, the one with the highest priority
T4_T0_REG_SEL_CNFG
MON_SW_PBO_CNFG
T0_INPUT_SEL_CNFG
T4_INPUT_SEL_CNFG
The
Register
No
priority
Monitoring). Locking allowance is con-
Locking Allowance
is
INn_VALID = '0',
(14 > n > 1)
set
Yes
by
December 9, 2008
the
Address (Hex)
corresponding
26 ~ 2C *
4C, 4D
4A, 4B
0B
50
51
07
WAN PLL