CY7B9911V-5JXC Cypress Semiconductor Corp, CY7B9911V-5JXC Datasheet - Page 5

IC CLK BUFF SKEW 8OUT 32PLCC

CY7B9911V-5JXC

Manufacturer Part Number
CY7B9911V-5JXC
Description
IC CLK BUFF SKEW 8OUT 32PLCC
Manufacturer
Cypress Semiconductor Corp
Type
Fanout Distribution, Zero Delay Bufferr
Series
RoboClock+™r
Datasheet

Specifications of CY7B9911V-5JXC

Number Of Circuits
1
Package / Case
32-PLCC
Pll
Yes
Input
LVTTL
Output
LVTTL
Ratio - Input:output
1:8
Differential - Input:output
No/No
Frequency - Max
110MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Frequency-max
110MHz
Output Frequency Range
3.75 MHz to 110 MHz
Supply Voltage (max)
3.63 V
Supply Voltage (min)
2.97 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-2240-5
CY7B9911V-5JXC

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Manufacturer
Quantity
Price
Part Number:
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Manufacturer:
CY
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23
Part Number:
CY7B9911V-5JXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
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Part Number:
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Figure 1
Test Mode
The TEST input is a three level input. In normal system
operation, this pin is connected to ground, allowing the
CY7B9911V to operate as described in
Description”
level inputs can have a removable jumper to ground or be tied
LOW through a 100Ω resistor. This enables an external tester to
change the state of these pins.
Document Number: 38-07408 Rev. *F
Note
4. FB connected to an output selected for “zero” skew (that is, xF1 = xF0 = MID).
shows the typical outputs with FB connected to a zero skew output.
(N/A)
(N/A)
(N/A)
(N/A)
1Fx
2Fx
MM
MH
HM
LM
LH
ML
HL
HH
LL
on page 4. For testing purposes, any of the three
LL/HH
(N/A)
(N/A)
(N/A)
(N/A)
3Fx
4Fx
MM
MH
HM
HH
LM
LH
ML
HL
Figure 1. The Typical Outputs with FB Connected to a Zero Skew Output
REFInput
FB Input
DIVIDED
INVERT
– 6t
– 4t
– 3t
– 2t
– 1t
+1t
+2t
+3t
+4t
+6t
0t
U
U
U
U
U
U
U
U
U
U
U
“Block Diagram
If the TEST input is forced to its MID or HIGH state, the device
operates with its internal phase locked loop disconnected, and
input levels supplied to REF directly control all outputs. Relative
output-to-output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW), all outputs
function based only on the connection of their own function
select inputs (xF0 and xF1) and the waveform characteristics of
the REF input.
[4]
3.3 V RoboClock+™
CY7B9911V
Page 5 of 17
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