TUA 6034 T Infineon Technologies, TUA 6034 T Datasheet - Page 27

• Manufacturer Part Number: TUA 6034 T
• Description: IC MIXER/OSC/PLL DIGITAL TSSOP38
• Manufacturer: Infineon Technologies

Specifications of TUA 6034 T

• Package / Case: 38-TSSOP
• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Frequency-max: *
• Bus Type: I2C
• Maximum Frequency: 863.25 MHz
• Minimum Frequency: 48.25 MHz
• Modulation Technique: FM
• Mounting Style: SMD/SMT
• Function: PAL, NTSC
• Noise Figure: 8 dB
• Operating Supply Voltage: 5 V
• Supply Voltage (min): 4.5 V
• Supply Voltage (max): 5.5 V
• Minimum Operating Temperature: - 20 C
• Maximum Operating Temperature: + 125 C
• Packages: PG-TSSOP-38
• Vs (min): 4.5 V
• Vs (max): 5.5 V
• Icc (max): 74.0 mA
• Esd Protection (max): 2.0 kV
• Mounting: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SP000013610; TUA 6034-T; TUA 6034-T; TUA6034TXT

TUA6034, TUA6036
TAIFUN
Functional Description
(acknowledge condition). The first byte is comprised of seven address bits. These are
used by the processor to select the PLL from several peripheral components (address
select). The LSB bit (R/W) determines whether data are written into (R/W = 0) or read
from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the first or
third data byte determines whether a divider ratio or control information is to follow. In
each case the second byte of the same data type has to follow the first byte. Appropriate
setting of the test bits will decide whether the band-switch byte or the auxiliary byte will
be transmitted
(see Table 11 Test modes on page
51).
If the address byte indicates a READ operation, the PLL generates an acknowledge and
then shifts out the status byte onto the SDA line. If the processor generates an
acknowledge, a further status byte is output; otherwise the data line is released to allow
the processor to generate a stop condition. The status word consists of three bits from
the A/D converter, the lock flag and the power-on flag.
Four different chip addresses can be set by an appropriate DC level at pin AS
(see
Table 10 Address selection on page
51).
While the supply voltage is applied, a power-on reset circuit prevents the PLL from
setting the SDA line to low, which would block the bus. The power-on reset flag POR is
set at power-on and if V
falls below 3.2 V. It will be reset at the end of a READ
CC
operation.
Specification
27
V 2.51, 2006-01-11