TUA 6034 T Infineon Technologies, TUA 6034 T Datasheet - Page 26

• Manufacturer Part Number: TUA 6034 T
• Description: IC MIXER/OSC/PLL DIGITAL TSSOP38
• Manufacturer: Infineon Technologies

Specifications of TUA 6034 T

• Package / Case: 38-TSSOP
• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Frequency-max: *
• Bus Type: I2C
• Maximum Frequency: 863.25 MHz
• Minimum Frequency: 48.25 MHz
• Modulation Technique: FM
• Mounting Style: SMD/SMT
• Function: PAL, NTSC
• Noise Figure: 8 dB
• Operating Supply Voltage: 5 V
• Supply Voltage (min): 4.5 V
• Supply Voltage (max): 5.5 V
• Minimum Operating Temperature: - 20 C
• Maximum Operating Temperature: + 125 C
• Packages: PG-TSSOP-38
• Vs (min): 4.5 V
• Vs (max): 5.5 V
• Icc (max): 74.0 mA
• Esd Protection (max): 2.0 kV
• Mounting: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SP000013610; TUA 6034-T; TUA 6034-T; TUA6034TXT

The software controlled ports P0 to P4 are general purpose open-collector outputs. The
test bits T2, T1, T0 =1, 0, 0 switch the test signals f
.4 MHz / 64) to P0 and P1 respectively.
The lock detector resets the lock flag FL if the width of the charge pump current pulses
is greater than the period of the crystal oscillator (i.e. 250 ns). Hence, if FL = 1, the
maximum deviation of the input frequency from the programmed frequency is given by
where I
frequency and C
the charge pump pulses at i.e. 62.5 kHz (= f
reset after the loop has lost lock state.
Once FL has been reset, it is set only if the charge pump pulse width is less than 250 ns
for eight consecutive f
set after the loop regains lock.
2.4.3
The wide band AGC stage detects the level of the IF output signal and generates an
AGC voltage for gain control of the tuners input transistors. The AGC take-over and the
time constant are selectable by the I
2.4.4
Data is exchanged between the processor and the PLL via the I
generated by the processor (input SCL). Pin SDA functions as an input or output
depending on the direction of the data (open collector, external pull-up resistor). Both
inputs have a hysteresis and a low-pass characteristic, which enhance the noise
immunity of the I
The data from the processor pass through an I
function the data are subsequently stored in registers. If the bus is free, both lines will be
in the marking state (SDA, SCL are high). Each telegram begins with the start condition
and ends with the stop condition. Start condition: SDA goes low, while SCL remains high.
Stop condition: SDA goes high while SCL remains high. All further information transfer
takes place during SCL = low, and the data is forwarded to the control logic on the
positive clock edge.
The table ’Bit Allocation’
referred to for the following description. All telegrams are transmitted byte-by-byte,
followed by a ninth clock pulse, during which the control logic returns the SDA line to low
Specification
f =
I
P
P
is the charge pump current, K
(K
AGC
I
2
VCO
C-Bus Interface
/ f
2
1
, C
C bus.
XTAL
2
the capacitances in the loop filter (see Chapter 3 on page 28). As
ref
) (C1+C2) / (C1 C2)
periods. Therefore it takes between 128 and 144 s for FL to be
(see Table 8 Bit Allocation Read/Write on page
2
C bus.
VCO
26
ref
), it takes a maximum of 16 s for FL to be
the VCO gain, f
2
C bus controller. Depending on their
div
(divided input signal) and f
Functional Description
Xtal
TUA6034, TUA6036
2
the crystal oscillator
C bus. The clock is
V 2.51, 2006-01-11
50) should be
TAIFUN
ref
(i.e