SI5368C-C-GQ Silicon Laboratories Inc, SI5368C-C-GQ Datasheet - Page 19

• Manufacturer Part Number: SI5368C-C-GQ
• Description: IC CLK MULTIPLIER ATTEN 100TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5368C-C-GQ

• Package / Case: 100-TQFP, 100-VQFP
• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Frequency-max: *
• Number Of Circuits: 1
• Maximum Input Frequency: 710 MHz
• Minimum Input Frequency: 0.002 MHz
• Output Frequency Range: 0.002 MHz to 346 MHz
• Supply Voltage (max): 2.75 V
• Supply Voltage (min): 1.71 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V, 2.5 V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

4. Register Descriptions
Reset value = 0001 0100
Register 0.
Name
Type
Bit
Bit
7
6
5
4
3
2
1
0
CK_CONFIG_
ALWAYS_ON
FREE_RUN
BYPASS_
Reserved
Reserved
Reserved
Reserved
CKOUT_
Name
D7
REG
REG
R
FREE_
Reserved.
Free Run.
Internal to the device, route XA/XB to CKIN2. This allows the device to lock to its external
reference.
0: Disable Free Run
1: Enable
CKOUT Always On.
This will bypass the SQ_ICAL function. Output will be available even if SQ_ICAL is on
and ICAL is not complete or successful. See Table 4.
0: Squelch output until part is calibrated (ICAL).
1: Provide an output. Note: The frequency may be significantly off until the part is
calibrated.
Reserved.
CK_CONFIG_REG.
This bit controls the input clock configuration for either normal CLKIN function or FSYNC
operation. Whenever CK_CONFIG_REG = 1, FSYNC_ALIGN_MODE must not be set to
1.
0: CKIN_1, 2, 3, 4 inputs do not have a synchronized relationship. CLKOUT5 is an inde-
pendent output. There is no FSYNCOUT.
1: CKIN_1, 3 and CKIN_2, 4 Clock/FSYNC pairs. CKOUT5 is configured as the FSYNC
output.
Reserved.
Bypass Register.
This bit enables or disables the PLL bypass mode. Use is only valid when the part is in
digital hold or before the first ICAL.
0: Normal operation
1: Bypass mode. Selected input clock is connected to CKOUT buffers, bypassing PLL.
Reserved.
RUN
R/W
D6
ALWAYS_
CKOUT_
R/W
ON
D5
Preliminary Rev. 0.41
D4
R
CONFIG_
Function
REG
CK_
R/W
D3
D2
R
BYPASS_
REG
R/W
D1
Si5368
D0
R
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