MAX3886ETN+ Maxim Integrated Products, MAX3886ETN+ Datasheet - Page 15

• Manufacturer Part Number: MAX3886ETN+
• Description: IC MULTIRATE CDR SER/DES56-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Clock and Data Recovery (CDR)r

Specifications of MAX3886ETN+

• Input: CML, LVDS
• Output: CMOS, LVDS
• Frequency - Max: 622MHz, 2.488GHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TQFN
• Frequency-max: 622MHz, 2.488GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 11. Three-State Input (MVCO)
Figure 12. LVCMOS Inputs
Figure 13. LVCMOS Outputs
Multirate CDR with Integrated Serializer/Deserializer
MSYM
MVCO
MDDR
FRST
______________________________________________________________________________________
MAX3886
V
V
CC
CC
V
CC
MAX3886
MAX3886
P
N
V
CC
V
V
CC
CC
P
N
P
N
for GPON and BPON ONT Applications
LOCK
FERR
A valid input at FRST is required to initialize the FIFO
after the relationship between PCKO or RCKO and PCKI
has stabilized prior to operating the serializer, or after the
FERR output has indicated that the FIFO has overflowed
or underflowed due to the phase difference between
PCKO or RCKO and PCKI exceeding its capacity. The
MAC IC provides the control signal for FRST. FERR
should not be directly connected to FRST.
If the PCKI signal is interrupted between bursts, the
FIFO must be reset before the beginning of each burst
while valid clocks are present. If a continuous PCKI sig-
nal is provided between bursts, the FIFO maintains the
correct FIFO counter values as long as the phase rela-
tionship does not change.
The integrated reference oscillator requires a parallel
resonant 19.4400MHz AT-strip cut crystal connected
between pins RFCK1 and RFCK2. It has 18pF nominal
(15pF to 21pF) of on-chip crystal load capacitance; any
frequency error due to mismatch to the rated crystal
load capacitance must be included in the budget for
the difference between reference clock frequency and
input data rate. Take care that the wiring capacitances
at the nodes RFCK1 and RFCK2 are controlled (typical-
ly no more than 2pF) to ensure proper operation.
To drive the reference clock with an external
19.4400MHz LVCMOS clock source, connect it to
RFCK1 through a 10pF ±10% series capacitor and
leave RFCK2 open. The LVCMOS clock source must be
capable of driving a 10pF load.
To ensure proper acquisition, the maximum difference
between the downstream data rate (divided down to
19.4400MHz) and 19.4400MHz clock should be
500ppm, including 57ppm required by the CDR itself.
Table 3 shows a typical budget.
Table 3. Typical Frequency Budget
Downstream Data Rate
Crystal Load Capacitance
Crystal Tolerance
Crystal Temperature Stability
Crystal Aging
CDR Operation
DESCRIPTION
Reference Clock Oscillator
Total
FIFO Control Signals
(±ppm)
100
395
50
63
75
50
57
f
G.983, G.984
e.g., 21ppm/pF
from 18pF
Total is less than
500ppm
NOTES
15