CY29976AXI Cypress Semiconductor Corp, CY29976AXI Datasheet - Page 3

• Manufacturer Part Number: CY29976AXI
• Description: IC CLK ZDB 12OUT 125MHZ 52LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Zero Delay Bufferr

Specifications of CY29976AXI

• Package / Case: 52-LQFP
• Frequency - Max: 125MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 125MHz
• Number Of Circuits: 1
• Maximum Input Frequency: 480 MHz
• Minimum Input Frequency: 200 MHz
• Output Frequency Range: 125 MHz
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 2.97 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Output: -
• Input: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Pin Definitions
Note
Document #: 38-07413 Rev. *D
2. A bypass capacitor (0.1F) must be placed as close as possible to each positive power (<0.2”). If these bypass capacitors are not close to the pins their high frequency
44, 46, 48, 50
32, 34, 36, 38
16, 18, 21, 23
35, 39, 47, 51
33,37, 45, 49
1, 15, 24, 30,
17, 22, 28,
filtering characteristics are cancelled by the lead inductance of the traces.
5, 26, 27
Pin No.
42, 43
40, 41
19, 20
11
12
10
29
25
52
31
14
13
9
6
7
8
2
3
4
PECL_CLK#
FB_SEL(2:0)
PECL_CLK
TCLK_SEL
SELC(1,0)
Pin Name
SELA(1,0)
SELB(1,0)
VCO_SEL
REF_SEL
INV_CLK
[2]
FB_OUT
MR#/OE
PLL_EN
QC(3:0)
QA(3:0)
QB(3:0)
TCLK0
TCLK1
SDATA
FB_IN
VDDC
SYNC
SCLK
VDD
VSS
PWR
V
V
V
V
V
DDC
DDC
DDC
DDC
DDC
IO
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
PU
PD
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PECL Clock Input.
PECL Clock Input.
External Reference/Test Clock Input.
External Reference/Test Clock Input.
Clock Outputs. See
Clock Outputs. See
Clock Outputs. See
Feedback Clock Output. Connect to FB_IN for normal operation. The
divider ratio for this output is set by FB_SEL(0:2). See
1. A bypass delay capacitor at this output controls Input Reference/
Output Banks phase relationships.
Synchronous Pulse Output. This output is used for system synchroni-
zation. The rising edge of the output pulse is in sync with both the rising
edges of QA (0:3) and QC(0:3) output clocks regardless of the divider
ratios selected.
Frequency Select Inputs. These inputs select the divider ratio at
QA(0:3) outputs. See
Frequency Select Inputs. These inputs select the divider ratio at
QB(0:3) outputs. See
Frequency Select Inputs. These inputs select the divider ratio at
QC(0:3) outputs. See
Feedback Select Inputs. These inputs select the divide ratio at FB_OUT
output. See
VCO Divider Select Input. When set LOW, the VCO output is divided
by 2. When set HIGH, the divider is bypassed. See
Feedback Clock Input. Connect to FB_OUT for accessing the PLL.
PLL Enable Input. When asserted HIGH, PLL is enabled. When LOW,
PLL is bypassed.
Reference Select Input. When HIGH, the PECL clock is selected. When
LOW, TCLK (0,1) is the reference clock.
TCLK Select Input. When LOW, TCLK0 is selected and when HIGH
TCLK1 is selected.
Master Reset/Output Enable Input. When asserted LOW, resets all of
the internal flip-flops and also disables all of the outputs. When pulled
HIGH, releases the internal flip-flops from reset and enables all of the
outputs.
Inverted Clock Input. When set HIGH, QC(2,3) outputs are inverted.
When set LOW, the inverter is bypassed.
Serial Clock Input. Clocks data at SDATA into the internal register.
Serial Data Input. Input data is clocked to the internal register to
enable/disable individual outputs. This provides flexibility in power
management.
3.3V Power Supply for Output Clock Buffers.
3.3V Supply for PLL
Common Ground
Table 1
Table 2
Table 2
Table 2
on page 1.
Table 2
Table 2
Table 2
on page 4 for frequency selections.
on page 4 for frequency selections.
on page 4 for frequency selections.
Description
on page 4.
on page 4.
on page 4.
Table 1
Table 1
CY29976
Page 3 of 9
on page 1.
on page
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