ICS950201AGLF IDT, Integrated Device Technology Inc, ICS950201AGLF Datasheet - Page 6

• Manufacturer Part Number: ICS950201AGLF
• Description: IC TIMING CTRL HUB P4 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS950201AGLF

• Input: Crystal
• Output: Clock
• Frequency - Max: 200MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1972-5; 950201AGLF; ICS950201AGLF

Byte 0: Control Register
Byte 1: Control Register
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways. Wither the
4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high, CPUCLKC
IDT
ICS950201
Programmable Timing Control Hub
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert PCI_STOP
functionality via I
In Hardware mode it is not allowed to write to the I
PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped PCI_STOP conditions.
The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it is not allowed to mix these
modes.
In Hardware mode the I
PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I
off, and external resistor termination will bring CPUCLKC low.
TM
B
B
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
t i
Programmable Timing Control Hub
0
2
3
4
5
6
7
0
2
3
4
5
6
7
1
1
4
4
4
4
5
5
P
P
, 9
, 5
, 9
, 5
, 2
, 2
4
4
5
5
3
5
3
n i
n i
-
-
-
4
5
0
4
3
5
3
4
4
4
4
5
5
#
#
8
4
8
4
1
1
2
C
C
C
C
C
C
C
C
C
C
C
3
C
C
M
P
C Byte 0 Bit 3.
V
P
P
P
P
C
P
P
P
P
P
P
P
P
P
U
E
N
6
U
U
U
U
U
S
U
U
U
U
U
U
_ I
U
U
N
L
6
n
a
p
C
C
F
F
C
C
C
C
C
C
T
F
_
C
C
C
C
a
S
_
a
-
m
e r
S
S
S
S
S
L
L
L
L
2
L
L
L
L
m
L
L
L
L
b
T
1
C byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip is in
K
K
K
K
0
2
T
K
K
K
K
E
1
e
K
K
a
e l
K
K
O
V /
e
O
C
C
C
C
d
T
T
T
T
L
C
C
T
T
d
P
C
0
0
2
0
2
P
0
2
0
2
1
1
1
1
#
H
#
3
TM
for P4
TM
P
P
W
for P4
X
W
0
0
0
0
1
1
1
X
X
X
X
X
0
0
0
1
D
TM
D
2
2
TM
2
C Byte 0 Bit3. In Software mode it is not allowed to pull the external
T
T
R
R
R
R
R
R
R
R
R
y
y
R
R
R
R
R
R
p
p
W
W
W
W
W
W
W
W
W
-
e
e
1
1
6
R
R
R
H
P
1
R
u r
u r
u r
R
p
p
p
S
0
C
V
0
(
0
0
0
0
A
f o
A
f o
A
f o
(
R
R
=
o
o
o
=
=
=
=
=
=
C
f e
f e
f e
a
f o
f e
C
o l l
o l l
o l l
f e
P
n
n
n
e
e
w
w
w
P
P
6
S
D
D
D
C
C
C
d r
_ I
U
H
n
n
n
e l
e l
e l
w t
e l
e l
s
s
6
w
w
w
r e
r e
r e
C
C
p
s i
s i
s i
P
P
P
n i
n i
n i
r e
r e
w
_
S
M
c
c
c
c
c
e r
S
a
C I
U
U
U
C I
a
a
a
S
c
c
c
g
g
g
s t
s t
s t
s t
s t
a
T
u
u
u
e v
e v
e r
e
H
b
b
b
o
o
o
a
_
_
_
T
e r
O
L
p
p
p
L
e l
e l
e l
e l
n
S
n
S
n
S
h t
h t
h t
h t
, z
d
h t
O
K
) d
) d
K
P
m
r t
r t
r t
t c
d
d
d
T
T
T
m
e
e
e
e
P
O
e
#
1
l o
l o
l o
n
o
s
O
O
O
1
1
1
#
o
=
, f f
6
a v
a v
a v
o t
t o
c
c
d
p
P
P
P
=
=
=
2
d
f o
f o
f o
r u
6
4
r u
: e
p
n i
C Byte 0 Bit 3 = 0)].
p
E
E
E
#
#
#
: e
1
u l
u l
u l
8
M
s
n i
p
e r
e r
=
M
n
n
n
C
C
C
o t
e
e
e
s
H
e
R
0
0
0
S
a
a
a
D
t n
t n
a
P
P
P
p
H
D
d
z
=
=
=
f o
f o
f o
b
b
b
f e
p
m
e
U
U
U
p
4 /
e
z
e l
e l
e l
N
N
N
e r
a v
a v
s
e l
e
p
C
C
C
s
F
F
F
8
d
d
d
o
o
o
c
d
e l
a
c
S
S
S
c
L
L
L
u l
u l
M
f t
f t
f t
i r
d
4
4
4
i r
s t
K
K
K
d
0
1
2
e
t p
e
H
e r
e r
e r
t p
T
T
T
O
o
p
p
p
h t
z
f o
f o
o i
0
e
1
e
2
e
n
o i
n i
n i
n i
n
C /
C /
C /
e
n
u r
u r
u r
h t
M
P
n
s
s
s
a v
0
1
2
W
n
n
n
a
a
a
e
U
n
n
n
m
m
m
u l
i w
i w
i w
L
D
x e
n i
n i
n i
T
p
p
p
e
h t
h t
h t
S
g
g
g
e t
e l
e l
e l
f o
E
n r
a
a
a
d
d
d
1
1
1
L
s s
s s
s s
=
=
=
o
o
o
l a
0
n
n
n
F
F
F
e
e
e
e r
e r
e r
t r
t r
t r
o i
o i
o i
e
e
e
n
n
n
460J—01/25/10