ICS9FG108DGILF IDT, Integrated Device Technology Inc, ICS9FG108DGILF Datasheet - Page 6

• Manufacturer Part Number: ICS9FG108DGILF
• Description: IC FREQ TIMING GENERATOR 48TTSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Frequency Generatorr

Specifications of ICS9FG108DGILF

• Input: Clock, Crystal
• Output: Differential
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1978-5; 9FG108DGILF; ICS9FG108DGILF

IDT
T
Operating Supply Current
Operating Supply Current
Input Rise and Fall times
1
2
3
4
these frequencies accordingly. The output frequecy selected by the FS inputs will also scale. For example, 27MHz
input with an FS selection of 100MHz will yield an output frequency of 27/25 x 100 = 108MHz.
Electrical Characteristics - Input/Supply/Common Output Parameters
ppm frequency accuracy on PLL outputs.
Guaranteed by design and characterization, not 100% tested in production.
See timing diagrams for timing requirements.
A
Input frequency should be measured at the REF pin and tuned to 0 PPM to meet
These values assume 25MHz or 14.31818MHz inputs respectively. Using a higher or lower frequency will scale
Spread Modulation %
Spread Modulation %
ICS9FG108D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
DIF_STOP# Current
DIF_STOP# Current
TM
= Tambient, Supply Voltage V
Input High Voltage
(T
Clk Stabilization
Spread Modulation
Input High Current
(T
Input Low Voltage
DIF output enable
Input Low Current
Input Frequency
(T
Pin Inductance
(T
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
A
PARAMETER
A
Capacitance
Input/Output
A
A
= Commercial)
= Commercial)
Frequency
= Industrial)
= Industrial)
1
1,2
1
3
IDD
IDD
IDD
SYMBOL
IDD
IDD
IDD
f
T
f
IDD
IDD
IDD
IDD
MOD%DWN
T
IDD
IDD
IDD
IDD
MOD%CTR
STABcom
t
C
STABind
f
DIFOE
t
V
L
C
V
I
I
MOD
VDDAPD
VDDAPD
VDDAPD
R
I
F
IL1
IL2
VDDPD
VDDPD
VDDPD
OUT
IH
pin
VDDA
VDDA
VDDA
VDDA
/t
IH
IN
IL
VDD
VDD
VDD
VDD
i
DD
F
= 3.3 V +/-5%
All DIF pairs stopped in driven
All DIF pairs stopped in driven
V
C
C
C
C
V
All DIF pairs stopped in Hi-Z
All DIF pairs stopped in Hi-Z
IN
L
L
L
L
From V
From V
IN
=Full load; fout = 400 MHz
=Full load; fout = 100 MHz
=Full load; fout = 400 MHz
=Full load; fout = 100 MHz
Center Spread Selected
DIF_Stop# de-assertion
Output pin capacitance
DIF output enable after
Down Spread Selected
= 0 V; Inputs with no pull-
= 0 V; Inputs with pull-up
20% to 80% of VDD
SEL14M_25M# = 0
SEL14M_25M# = 1
SEL14M_25M# = 0
SEL14M_25M# = 1
CONDITIONS
Logic Inputs
3.3 V +/-5%
3.3 V +/-5%
up resistors
DD
DD
V
resistors
IN
Power-Up to 1st
Power-Up to 1st
mode
mode
mode
mode
clock
clock
= V
DD
6
V
22.50
12.89 14.31818
SS
-200
MIN
1.5
-5
-5
2
- 0.3
32.541
32.467
25.00
TYP
186
156
148
205
172
163
22
22
22
30
22
24
24
24
33
24
SPEC
V
+/-0.25
28.00
15.75
MAX
DD
-0.5
215
179
170
236
198
187
0.8
1.8
25
25
25
35
25
28
28
28
38
28
15
5
7
5
6
3
5
+ 0.3
UNITS NOTES
MHz
MHz
kHz
kHz
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ms
ms
uA
uA
uA
nH
pF
pF
ns
ns
%
%
V
V
1,3,4
1,3,4
1,3,4
1,3,4
1,2
1,2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
3
1
1
1
1
1
1542E 12/16/10