ICS9FG108DGILF IDT, Integrated Device Technology Inc, ICS9FG108DGILF Datasheet - Page 13

• Manufacturer Part Number: ICS9FG108DGILF
• Description: IC FREQ TIMING GENERATOR 48TTSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Frequency Generatorr

Specifications of ICS9FG108DGILF

• Input: Clock, Crystal
• Output: Differential
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1978-5; 9FG108DGILF; ICS9FG108DGILF

IDT
DIF_STOP# - De-assertion (transition from '0' to '1')
With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the
de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of
interest is programmed to '1', then the stopped DIF outputs will be driven High within 15nS of DIF_Stop# de-assertion to a
voltage greater than 200mV.
Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the SMBus
DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True =
HIGH and DIF_Complement = LOW. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is
programmed to a '1', DIF outputs will be tri-stated.
ICS9FG108D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
DIF_STOP# - Assertion (transition from '1' to '0')
TM
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
DIF_STOP#
DIF#
DIF
DIF Internal
DIF_Stop#
DIF#
DIF
Tdrive_DIF_Stop, 15nS >200mV
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