NBSG111BAG ON Semiconductor, NBSG111BAG Datasheet - Page 3

• Manufacturer Part Number: NBSG111BAG
• Manufacturer: ON Semiconductor
• Type: Clock Driverr

Specifications of NBSG111BAG

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Logic Level: ECL
• Operating Supply Voltage (min): -2.375/2.375V
• Operating Supply Voltage (typ): -2.5/-3.3/2.5/3.3V
• Operating Supply Voltage (max): -3.465/3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Table 1. PIN DESCRIPTION
1. In the differential configuration when the input termination pins (VTCLK, VTDCLK) are connected to a common termination voltage and
C1,E1,G2,G4,G6,E7,
B1,D1,F1,G3,G5,F7,
A1,A7,G1,G7,C2,E6
if no signal is applied, then the device will be susceptible to self−oscillation.
D7,B7,A5,A3
C7,A6,A4,A2
F3,D4,B5
F2,B6
Pin
C4
C3
D5
D6
C5
C6
D3
D2
B2
F6
E4
F4
E5
F5
B4
B3
E3
E2
VTCLK0
VTCLK0
VTCLK1
VTCLK1
VTSEL
VTSEL
Name
Q[0:9]
Q[0:9]
VTEN
VTEN
CLK0
CLK0
CLK1
CLK1
V
SEL
SEL
V
V
V
NC
EN
EN
MM
EE
CC
BB
ECL, CML, LVCMOS, LVDS,
ECL, CML, LVCMOS, LVDS,
ECL, CML, LVCMOS, LVDS,
ECL, CML, LVCMOS, LVDS,
ECL, CML, LVCMOS, LVDS,
ECL, CML, LVCMOS, LVDS,
ECL, CML, LVCMOS, LVDS,
ECL, CML, LVCMOS, LVDS,
RSECL Output
RSECL Output
LVTTL Input
LVTTL Input
LVTTL Input
LVTTL Input
LVTTL Input
LVTTL Input
LVTTL Input
LVTTL Input
I/O
−
−
−
−
−
−
−
−
−
−
−
−
−
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3
Negative Supply Voltage. All V
ted to Power Supply to Guarantee Proper Operation.
Positive Supply Voltage. All V
to Power Supply to Guarantee Proper Operation.
LVCMOS Reference Voltage Output (V
ECL Reference Voltage Output
Internal 50 W Termination Pin for CLK0. See Table 4. (Note 1)
Noninverted Differential Input CLK0. Internal 75 kW to V
Internal 50 W Termination Pin for CLK0. See Table 4. (Note 1)
Inverted Differential Input CLK0. Internal 75 kW to V
to V
Internal 50 W Termination Pin 1. See Table 4. (Note 1)
Noninverted Differential Input CLK1. Internal 75 kW to V
Internal 50 W Termination Pin for CLK1. See Table 4. (Note 1)
Inverted Differential Input CLK1. Internal 75 kW to V
to V
Noninverted Differential Outputs [0:9]. Typically Terminated with
50 W to V
Inverted Differential Outputs [0:9]. Typically Terminated with 50 W to
V
Internal 50 W Termination Pin for SEL. See Table 4. (Note 1)
Noninverted Differential Select Logic Input. Internal 75 kW to V
Internal 50 W Termination Pin for SEL. See Table 4. (Note 1)
Inverted Differential Select Logic Input. Internal 75 kW to V
36.5 kW to V
Internal 50 W Termination Pin for EN. See Table 4. (Note 1)
Noninverted Differential Output Enable Pin. Internal 75 kW to V
Internal 50 W termination Pin for EN. See Table 4. (Note 1)
Inverted Differential Output Enable Pin. Internal 75 kW to V
36.5 kW to V
No Connect. The NC Pins are Electrically Connected to the Die and
”MUST BE” Left Open.
TT
CC
CC
= V
.
.
CC
TT
− 1.5 V
= V
CC
CC
.
.
CC
− 1.5 V
Description
CC
EE
Pins Must be Externally Connected
Pins Must be Externally Connec-
CC
− V
EE
) / 2.
EE
EE
and 36.5 kW
and 36.5 kW
EE
EE
.
.
EE
EE
and
and
EE
EE
.
.