TLE6244XXT Infineon Technologies, TLE6244XXT Datasheet
TLE6244XXT
Specifications of TLE6244XXT
Related parts for TLE6244XXT
TLE6244XXT Summary of contents
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... Channel Smart Lowside Switch ASSP for Powertrain Final Data Sheet Features • Short Circuit Protection • Overtemperature Protection • Overvoltage Protection • 16 bit Serial Data Input and Diagnostic Output (2 bit/chan. acc. SPI Protocol) • Direct Parallel Control of 16 channels for PWM Applications • ...
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... Serial transmission of the error code via SPI. 1.1.3 VDD-Monitoring Low signal at pin ABE and shut-off of the power stages if VDD is out of the permitted range. Exception: If OUT8 is controlled by IN8, OUT8 will only be switched off by the overvoltage detection and not by undervoltage detection. The state of VDD can be read out via SPI. ...
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Block Diagram fault diagnostics IN1 SPI IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12 IN13 IN14 IN15 IN16 control only via SPI possible control only via SPI possible IN6 IN7 IN16 µsec - Bus SCK SPI ...
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... An integrated zener diode limits the output voltage to 45V typically. OUT7, OUT8, OUT17, OUT18 4 low side power switches for nominal currents up to 1100mA. Stage 7 is non-inverting, Stage 8 is inverting (IN8 = ‘1’ => OUT8 is active). For the output OUT7 control is possible by the input pin, by the µ ...
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... IN8 this power stage is functional if the voltage at the pin VDD is above 3,5V. In SPI mode the power stage is fully supervised by the VDD-monitor. If OUT8 is controlled by IN8, OUT8 will only be switched off by the overvoltage detection and not by undervoltage detection. 1.3.1.2 Phase Relation IN8 - OUT8 The phase relation IN8 -> ...
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Pinout Function Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 or FDA Input 7 or SSY Input 8 Input 9 Input 10 Input 11 Input 12 Input 13 Input 14 Input 15 Input 16 or ...
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Supply Voltage VDD Supply Voltage U att B GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 Sense Ground VDD-Monitoring In-/Output VDD-Monitoring Reset (low active) not connected IN15 1 OUT15_1 2 OUT15_2 3 OUT11 4 IN11 5 IN5 6 IN1 7 ...
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... Ground pins for the power stages (see 2.4) Ground reference of all logic signals is GND1/2 RST Reset Active low Locks all power switches regardless of their input signals (except OUT8) Clears the fault registers Resets the µsec-bus interface registers ABE In-/Output VDD-Monitoring Active low ...
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SPI Interface The serial SPI interface establishes a communication link between TLE6244X and the systems mi- crocontroller. TLE6244X always operates in slave mode whereas the controller provides the mas- ter function. The maximum baud rate is 5 MBaud. The ...
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... Characteristics of the SPI Interface the slave select signal High, the SPI-logic is set on default condition, i.e. it expects an instruction the 5V-reset (RST) is active, the SPI output SO is switched into tristate. The VDD monitoring (ABE) has no influence on the SPI interface. 3) Verification byte: Simultaneously to the receipt of an SPI instruction TLE6244X transmits a verification byte via the output SO to the controller ...
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INSW afterwards is wrong) but modifications on any register of TLE6244 are not allowed until bit INSW is valid, too. If ...
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SPI Instructions SPI Instruction bit 7,6 CPAD1,0 RD_IDENT1 RD_IDENT2 WR_STATCON WR_MUX1 WR_MUX2 WR_SCON1 WR_SCON2 WR_SCON3 WR_CONFIG RD_MUX1 RD_MUX2 RD_SCON1 RD_SCON2 RD_SCON3 RD_STATCON DEL_DIA RD_DIA1 RD_DIA2 RD_DIA3 RD_DIA4 RD_DIA5 RD_CONFIG RD_INP1 RD_INP2 Final Data Sheet Encoding bit 5,4,3,2,1 Parity INSTR(4...0) 00 ...
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Serial/Parallel Control Serial/Parallel Control of the Power Stages 1...16 and Serial Control (SPI) of the Power Stages 17 and 18: The registers MUX_REG1/2 and the bmux-bit prescribe parallel control or serial control (SPI or µsec- bus) of the power ...
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Description of the SPI Registers Register: MUX_REG1 7 6 MUX7 MUX6 State of Reset: 80H Access by Controller: Bit Name 0 MUX0 1 MUX1 2 MUX2 3 MUX3 4 MUX4 5 MUX5 6 MUX6 7 MUX7 Register: MUX_REG2 7 6 ...
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Register: SCON_REG1 7 6 SCON7 SCON6 State of Reset: FFH Access by Controller: Bit Name 0 SCON0 1 SCON1 2 SCON2 3 SCON3 4 SCON4 5 SCON5 6 SCON6 7 SCON7 Register: SCON_REG2 7 6 SCON15 SCON14 State of Reset: ...
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Register: SCON_REG3 State of Reset: FFH Access by Controller: Bit Name 0 SCON16 1 SCON17 7-2 Final Data Sheet Read/Write Description State of serial control of power stage 17 State ...
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Diagnostics/Encoding of Failures Description of the SPI Registers (SPI Instructions: RD_DIA1...5) Register: DIA_REG1 7 6 DIA7 DIA6 State of Reset: FFH Access by Controller: Bit Name 1-0 DIA (1-0) 3-2 DIA (3-2) 5-4 DIA (5-4) 7-6 DIA (7-6) Register: ...
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Register: DIA_REG3 7 6 DIA23 DIA22 State of Reset: FFH Access by Controller: Bit Name 1-0 DIA (17-16) 3-2 DIA (19-18) 5-4 DIA (21-20) 7-6 DIA (23-22) Register: DIA_REG4 7 6 DIA31 DIA30 State of Reset: FFH Access by Controller: ...
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Register: DIA_REG5 State of Reset: FFH Access by Controller: Bit Name 1-0 DIA (33-32) 3-2 DIA (35-34) 4 UBatt 7-5 Encoding of the Diagnostic Bits of the Power Stages DIA(2*x- Final Data ...
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... The output is not switched off in case of SCB 1: The output OUT10 is switched off in case of SCB 0: The output is not switched off in case of SCB 1: The output OUT15 is switched off in case of SCB 0: The output is not switched off in case of SCB 1: The output OUT16 s switched off in case of SCB ...
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Other Reading the IC Identifier (SPI Instruction: RD_IDENT1): IC Identifier1 (Device ID ID7 ID6 Bit Name 7...0 ID(7...0) Reading the IC revision number (SPI Instruction: RD_IDENT2): IC revision number 7 6 SWR3 SWR2 Bit Name 7...4 SWR(3...0) ...
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Final Data Sheet 22 TLE 6244X V4.2, 2003-08-29 ...
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Final Data Sheet 23 TLE 6244X V4.2, 2003-08-29 ...
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Final Data Sheet 24 TLE 6244X V4.2, 2003-08-29 ...
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Final Data Sheet 25 TLE 6244X V4.2, 2003-08-29 ...
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Final Data Sheet 26 TLE 6244X V4.2, 2003-08-29 ...
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Reading Input1 (SPI Instruction: RD_INP1) : Register INP_REG1 7 6 IN8 Test Bit Name 0..4 IN(1... Test 7 IN8 Reading Input2 (SPI Instruction: RD_INP2): Register INP_REG2 IN15 Bit Name 0..6 IN9...IN15 7 The input pins ...
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... RST = Low or undervoltage at VDD (see 3.2. )) State of Reset: 1 Access by Controller: Bit = 1: Latch function for overvoltage at VDD is switched on Bit = 0: Latch function for overvoltage at VDD is switched off State of Reset: 1 Access by Controller: 28 TLE 6244X 2 ...
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... Bit = 1: Lower threshold of VDD-monitoring is lifted if bit CONFIG2 = 0 (test of switch-off path) Bit = 0: Upper threshold of VDD-monitoring is reduced if bit CONFIG2 = 0 (test of switch-off path) State of Reset: 1 Access by Controller: Read/Write Bit = 1: Test of VDD threshold is switched off Bit = 0: Test of VDD threshold is switched on State of Reset: 1 Access by Controller: Read/Write 29 TLE 6244X V4.2, 2003-08-29 ...
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... The µsec-bus-interface is one of three possibilities to control the power stages. OUT1...OUT7 and OUT9...OUT16 are influenced by the reset input RST. If RST is set to Low, these power stages are switched off. After reset they are controlled by the SPI (default initialization of TLE6244X). Power stage 8 however is not influenced by the reset input if it’s controlled by IN8 and U > ...
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... When the bit BMUX in CONFIG is set to Low, the power stages 1...7 and 9...16 are controlled by the µsec-bus-interface on condition that registers MUX_REG1/2 are configured for serial access. The received µsec-bus bit stream (D0... D15) is latched into a 16-bit register by the rising edge at SSY. Power stages 1...7 and 9...16 are switched according to bits D0...D7 and D9...D15: µsec-bus D0 ...
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... Unused Power Stages To avoid an „open load“ fault indication an unused power switch has to be connected to an exter- nal pull up resistor connected to U µsec-bus-interface. U UBatt UBR R Pull-up,max UBR is the required minimum battery voltage for diagnostic function of the ECU. The drop volt- ...
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Timing Diagram of the Power Outputs 1.9.1 Power Stages U INi U INiH U INiL U OUTi U CLi 0.8U *) CLi U BATT 0.8U BATT 0.2U CLi 0.2U BATT If the output is controlled via SPI the timing ...
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... TLE6244X are switched off. Exception: OUT8 is not switched off in case of parallel control via IN8 by the VDD monitoring undervoltage threshold, but by a threshold of 3.5V at VDD. On shorting pin ABE UBATT ( 36V), the power stages will be switched off in case of undervoltage or overvoltage at pin VDD in spite of ABE = high. ...
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Bit overvoltage at pin VDD 0: overvoltage at pin VDD resp. state of overvoltage still stored Access by controller: read only Testing the VDD-Monitoring: Upper threshold: By writing 000xxxxx b in the register STATCON_REG the overvoltage threshold ...
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Final Data Sheet 100k 36 TLE 6244X <= <= V4.2, 2003-08-29 ...
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... The power stages 7...18 are equipped with a 40V active clamping. Therefore this power stages must only drive loads with an accordingly high resistance that can be switched on in case of over- voltage (e.g. a maximum load dump voltage of 60V and a load resistor of 1k dissipation of 0 ...
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Notes for the Diagnostics - SCB entry in DIA_REGx see diagrams in chapter 1.6. case of overvoltage at pin VDD (VDD > 5,5V) the diagnostic information can be wrong. In that case, the diagnostic information has to ...
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State Diagram of the Power Stages Diagnostics Final Data Sheet 39 TLE 6244X V4.2, 2003-08-29 ...
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... Parallel Connection of Power Stages The power stages (PS) which are connected in parallel have to be switched on and off simultaneously. The corresponding SPI-Bits SCONx have the same register (see page 15), when the PS are serial controlled via SPI. In case of overload the ground current and the power dissipation are increasing. The application has to take into account that all maximum ratings are observed (e ...
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For every PS there exists only one symmetrical PS OUT1 and OUT2 are symmetrical PS. OUT3 and OUT4 are symmetrical PS. ... OUT17 and OUT18 are symmetrical PS. note the same type have the same ...
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... C) Guaranteed by design (covered by lab tests, not considered within the standard production flow) 2.3 Thermal Limits Operating temperature TLE6244 continuous additionally only for the power switches (for 100h accumulated) Storage temperature Thermal resistance 2.4 Electrical Limits Limits must absolutely not be exceeded. By exceeding only one limit the integrated circuit might be destroyed ...
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... Therefore it is advisable to short-circuit the 4 ground pins on the PCB and to connect them with the heat sink. In addition the 4 ground pins GND5..8 must be connected to the other ground pins on the PCB Inputs of the Power Switches, SPI Inputs, Reset and Shut-off of the Power Stages Input voltage Input currents ...
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... Parameters 4.5V 4.5V TLE6244: -40°C unless otherwise noted. If VDD-monitoring is active the power stages are switched off except OUT8 (see page 28). Positive current flows into the pin, negative current flows out of the pin. Unless otherwise noted all volt- ages are referred to GND (GND1 ...
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... U UBatt = 14V U UBatt = 28V U UBatt Power consumption in standby mode in case of missing U VDD, U UBatt 3.4 Inputs of the Outputs are switched off if inputs Power Stages are open (parallel control). and Reset IN1...IN16, RST 3.4.1 Low Level Reset not active, Power stage on for ...
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... Above this limit short circuit to UBatt is detected. For the duration of the shutoff delay time t 3.5.4) the output current is limited to approximately this value. If the short circuit condition is still present after t switched off. An error is stored after t Final Data Sheet > 2.2A U 17V UBatt > 21V ...
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... Between 17V short circuit shutdown threshold is switched. A power stage that is switched off in case of SCB can be switched on again by an off/on cycle at the cor- responding input pin resp. by the change of the state of the corre- sponding SPI bit SCONx (see page 16), by the µsec-Bus DEL_DIA instruction or can be released again by reset ...
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Leakage Cur- U VDD rent age current of the DMOS, diag- nostic current = 0) U VDD age current of the DMOS, diag- nostic current = 0) 3.5.8 Clamping 3.5.8.1 Clamping I OUT1...6 Voltage 3.5.8.2 Matching of Between different ...
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... Power outputs In case of open input (parallel con- 2.2A/45V trol) or missing power supply the OUT9...OUT14 power stage is switched off. Paral- lel connection of power stages is possible. 3.6.1 Nominal Cur- rent 3.6.2 Extended Cur- I > 2.2A OUTi rent Range Accumulated operating time 3 ...
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... A power stage that is switched off in case of SCB can be switched on again by an off/on cycle at the cor- responding input pin resp. by the change of the state of the corre- sponding bit for SPI or µsec-bus by a DEL_DIA instruction or can be released again by reset. If the fault register is cleared before this ...
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... On /off Delay „On“ Times „Off“ (Measurement with ohmic load don switch-on slew rate switch-off slew rate 3.6.7 Leakage Cur- U VDD rent (leakage current of the DMOS, diagnostic current = 0) U VDD (leakage current of the DMOS, diagnostic current = 0) 3.6.8 Clamping 3.6.8.1 Clamping ...
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... UBatt is detected. For the duration of the shutoff delay time t 3.6.4) the output current is limited to approximately this value. If the short circuit condition is still present after t OUT15/16 are switched off if the static current limitation is not enabled. An error is stored after t (see 3.11.4). Diag Above this limit short circuit to UBatt is detected ...
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... UBatt up to 20%. 3.7.6 On /off Delay „On“ Times „Off“ (Measurement with ohmic load don switch-on slew rate switch-off slew rate 3.7.7 Leakage Cur- U VDD rent (leakage current of the DMOS, diagnostic current = 0) U VDD (leakage current of the DMOS, diagnostic current = 0) 3.7.8 Clamping 3 ...
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... If the short circuit condition is still present after t OUT7/8 are switched off. An error is stored after t The same is true for OUT17 OUT18 if the static current limita- tion is not enabled. Final Data Sheet = 2 over the load, e ...
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... Between 17V short circuit shutdown threshold is switched for OUT7/8 A power stage that is switched off in case of SCB can be switched on again by an off/on cycle at the cor- responding input pin resp. by the change of the state of the corre- sponding bit for SPI or µsec-bus by a DEL_DIA instruction or can be released again by reset ...
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... J 3.8.6 On/off Delay „On“ Times „Off“ (Measurement with ohmic load don Switch-on slew rate Switch-off slew rate 3.8.7 Leakage Cur- For OUT7,8, OUT1718: rent U VDD current of the DMOS, diagnostic current = 0) U VDD current of the DMOS, diagnostic current = 0) 3 ...
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Maximum Each output 75% of the values of Clamping En- 3.8.8.2 resp. 3.8.8.3. ergy with two Outputs con- nected in par- allel 3.8.8.5 Maximum For a maximum of 10 times during Clamping En- ECU life (load dump with 400ms ...
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SPI Interface The timing of TLE6244X is defined as follows: - The change at output (SO) is forced by the rising edge of the SCK signal. - The input signal (SI) is sampled on the falling edge of the ...
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Input SCK SPI clock input 3.9.1.1 Low Level 3.9.1.2 High Level 3.9.1.3 Hysteresis 3.9.1.4 Input Capacity 3.9.1.5 Input Current Pull up current source connected to VDD 3.9.2 Input SS Slave select signal 3.9.2.1 Low Level TLE6244X is selected 3.9.2.2 ...
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Timing 1. Cycle-Time (referred to master) 2. Enable Lead Time (referred to master) 3. Enable Lag Time (referred to master) 4. Data Valid CL = 50pF (5 MHz) Data Valid CL = 200pF (2MHz) (referred to TLE6244X) 5. Data ...
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... Low Level 3.10.1.2 High Level 3.10.1.3 Hysteresis 3.10.1.4 Input Ca- pacity 3.10.1.5 Input Cur- Pull up current source connected rent to VDD 3.10.2 Timing Cycle Time Data setup time Data hold time Switching time on FCL f FCL < 10MHz Final Data Sheet t cyc t setup t hold t shold ...
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... Switching time on FCL f FCL > 10MHz Select hold time FCL Low time FCL High time SSY Low time SSY High time Time between rising edge of SSY and next falling edge of FCL 3.11 Diagnostics 3.11.1 Diagnostic Thresholds Power Stages 3.11.1.1 Open Load Output turned off (OL) 3 ...
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... Filtering Time from occurrence of one of Time Power the errors ’short to ground’, ’open Switches load’ or ’short to battery’ until the fault is entered into the corre- sponding diagnostic register. Time from occurrence of OT until the information is entered into the corresponding diagnostic register. ...
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VDD-Monitor- Bidirectional: open drain output / ing ABE input with pull up current source An external current limitation must guarantee I ABE < for any U ABE 3.13.1 Output U ABE 2.7V < U 5.3V... 5.5V < ...
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... Permissible Offset be- tween GND_ABE and GND 3.13.8.2 Bond Lift / Pin ABE goes LOW Solder Crack (see 3.13.1.1). on The power stages are switched off. GND_ABE The over- and undervoltage thresholds are increased by typi- cally 700mV for T Final Data Sheet B V DDth_l B ...
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Clamping Energy 3.14 f(I ), 2.2A Power Stages with 70V Clamping OUT1... 3.14 2.2A Power Stages with 45V Clamping OUT9...A14 ...
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E = f(I ), 1100mA Power Stages with 45V Clamping OUT7,8,17, 3.14 f(I ), 3.0A Power Stages with 45V Clamping OUT15, OUT16 ...
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ESD All pins of the IC have to be protected against electrostatic discharge (ESD) by appropriate pro- tection components. The integrated circuit has to meet the requirements of the „Human Body Model“ with 100pF and R2 ...
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Package Outline Final Data Sheet 69 TLE 6244X V4.2, 2003-08-29 ...
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... Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system ...