AD6622AS Analog Devices Inc, AD6622AS Datasheet - Page 11

• Manufacturer Part Number: AD6622AS
• Manufacturer: Analog Devices Inc

Specifications of AD6622AS

• Lead Free Status / RoHS Status: Not Compliant

The serial data frame sync output, SDFS, is pulsed high for one
SCLK cycle at the input sample rate. The input sample rate is
determined by the master clock divided by channel interpolation
factor. If the SCLK rate is not an integer multiple of the input
sample rate, the SDFS will continually adjust the period by one
SCLK cycle in order to keep the average SDFS rate equal to the
input sample rate. When the channel is in sleep mode, SDFS is
held low. The first SDFS is delayed by the channel reset latency
after the Channel Reset is removed. The channel reset latency
varies dependent on channel configuration.
The serial data input, SDIN, accepts 32-bit words as channel
input data. The 32-bit word is interpreted as two 16 bit two’s
complement quadrature words, I followed by Q, MSB first.
The first bit is shifted into the serial port starting on the second
rising edge of SCLK after SDFS goes high, as shown by the
timing diagram below.
As an example of the serial port operation, consider a CLK fre-
quency of 62.208 MSPS and a channel interpolation of 2560.
In that case, the input sample rate is 24.3 kSPS (62.208 MSPS/
2560), which is also the SDFS rate. Substituting, f
f
we find the maximum value for SCLK
Equation 2.
Evaluating this equation for our example, SCLK
less than or equal to 39. Since the SCLK
ter is a 5-bit unsigned number it can only range from 0 to 31.
Any value in that range will be valid for this example, but if it is
important that the SDFS period is constant, then there is another
restriction. For regular frames, the ratio f
to an integer of 32 or larger. For this example, constant SDFS
periods can only be achieved with an SCLK divider of 19.
In conclusion, the SDFS rate is determined by the AD6622 master
clock rate and the interpolation rate of the channel. The SDFS
rate is equal to the channel input rate. The channel interpola-
tion is equal to RCF interpolation times CIC5 interpolation,
times CIC2 interpolation
The SCLK rate is determined by the AD6622 master clock
rate and SCLK
AD6622 master CLK. The SCLK divide ratio is determined by
SCLK
enough to input 32 bits of data prior to the next SDFS. Extra
SCLKs are ignored by the serial port.
SCLK
SDFS
SDFS
CLK
SDI
SCLK
L
into the equation below and solving for SCLK
DIVIDER
=
L
RCF
t
DSCLK
DIVIDER
t
DSDFS
as shown in Equation 2. The SCLK must be fast
×
DIVIDER
L
CIC
≤
5
64
×
. The SCLK is a divided version of the
×
L
f
CLK
CIC
t
f
DSDFS
SDFS
t
SSI
2
DATAn
–
1
CLKn
t
HSI
SCLK
DIVIDER
DIVIDER
/f
SDFS
DIVIDER
according to
channel regis-
must be equal
SCLK
DIVIDER
must be
≥ 32 ×
,
(2)
(3)
PROGRAMMABLE INTERPOLATING RAM
COEFFICIENT FILTER (RCF)
Each channel has a fully independent RAM Coefficient Filter
(RCF). The RCF accepts data from the serial port, filters it, and
passes the result to the CIC filter. The RCF implements a FIR
filter with optional interpolation. The FIR filter can produce
impulse responses up to 128 output samples long. The FIR
response may be interpolated up to a factor of 128, although
the best filter performance is usually achieved if the RCF inter-
polation factor is confined to 8 or below.
FIR Filter Implementation
The RCF accepts quadrature samples from the serial port with a
fixed point resolution of 16 bits each, for I and Q.
The AD6622 RCF realizes a sum-of-products filter using a poly-
phase implementation. This mode is equivalent to an interpola-
tor followed by a FIR filter running at the interpolated rate. In
Figure 12, the interpolating block increases the rate by the RCF
interpolation factor (L
between every input sample. The next block is a filter with a finite
impulse response length (N
where n is an integer from 0 to N
The difference equation for Figure 12 is written below, where
h[n] is the RCF impulse response, b[n] is the interpolated input
sample sequence at point “b” in Figure 12, and c[n] is the out-
put sample sequence at point “c” in the Figure 12.
This difference equation can be described by the transfer func-
tion from point “b” to “c” as shown Equation 5.
The actual implementation of this filter uses a polyphase
decomposition to skip the multiply-accumulates when b[n] is
zero. Compared to the diagram above, this implementation has
the benefits of reducing by a factor of L
calculate an output and the required data memory (DMEM). The
price of these benefits is that the user must place the coefficients
into the coefficient memory (CMEM) indexed by the interpo-
lation phase. The process of selecting the coefficients and placing
them into the CMEM is broken into three steps shown below.
SDFS
SCLK
SDIN
c n
H z
[ ]
bc
( )
=
SERIAL
PORT
N
f
IN
= ∑
a
k
RCF
∑
=
N
0
−
n
1
RCF
=
h k n
0
[
−
1
COEFFICIENT
L
h n
RCF
−
[ ]
RCF
DATA
MEM
MEM
]
16,16
) by inserting L
×
16,16
×
RCF
z
f
IN
b n
−
[ ]
n
) and an impulse response of h[n],
b
L
RCF
RCF
ACCUMULATOR
FIR FILTER
N
-1.
RCF
RCF
h[n]
RCF
TAP
both the time needed to
-1 zero valued samples
f
IN
c
RCF COARSE
RCF
AD6622
L
SCALE
RCF
16,16
IQ TO
CIC
FILTER
(4)
(5)