AD6622AS Analog Devices Inc, AD6622AS Datasheet

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AD6622AS

Manufacturer Part Number
AD6622AS
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD6622AS

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AD6622AS
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PRODUCT DESCRIPTION
The AD6622 comprises four identical digital Transmit Signal
Processors (TSPs) complete with synchronization circuitry and
cascadable wideband channel summation. An external digital-
to-analog converter (DAC) is all that is required to complete a
wide band digital up-converter. On-chip tuners allow the relative
phase and frequency for each RF carrier to be independently
controlled.
Each TSP has three cascaded signal processing elements: a
RAM-programmable Coefficient interpolating Filter (RCF), a
programmable Cascaded Integrator Comb (CIC) interpolating
filter, and a Numerically Controlled Oscillator/tuner (NCO).
The outputs of the four TSPs are summed and scaled on-chip.
Transmit Signal Processor (TSP)
In multichannel wideband transmitters, multiple AD6622s may
be combined using the chip’s cascadable output summation stage.
Each channel provides independent serial data inputs that may
be directly connected to the serial port of DSP chips. User pro-
grammable FIR filters can be used to filter linear inputs.
All control registers and coefficient values are programmed through
a generic microprocessor interface. Two microprocessor bus
modes are supported. All inputs and outputs are LVCMOS
compatible. All outputs are LVCMOS and 5 V TTL compatible.
Four-Channel, 75 MSPS Digital
CH A
CH B
CH C
CH D
SPORT
SPORT
SPORT
SPORT
FUNCTIONAL BLOCK DIAGRAM
JTAG
RCF
RCF
RCF
RCF
FILTER
FILTER
FILTER
FILTER
CIC
CIC
CIC
CIC
PORT
NCO
NCO
NCO
NCO
AD6622
18
18

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AD6622AS Summary of contents

Page 1

PRODUCT DESCRIPTION The AD6622 comprises four identical digital Transmit Signal Processors (TSPs) complete with synchronization circuitry and cascadable wideband channel summation. An external digital- to-analog converter (DAC) is all that is required to complete a wide band digital up-converter. ...

Page 2

... IV 25°C V Full Full IV VDD – 0.05 Full IV Full Full IV Full Full IV AD6622AS Typ Max Unit 3.0 3.3 V °C +25 +70 AD6622AS Typ Max Unit 3.0 V CMOS VDD + 0.3 V +0.8 V µ µ VDD – 0.035 V 0.02 0. 506 566 mA 2 297 mA 2 240 mA 2 ...

Page 3

... IV Full IV Full IV Full IV Full IV Full IV Full IV Full IV Full IV Full IV Full IV Full IV Full IV Full IV Full IV Full IV Full IV Full IV AD6622 AD6622AS Min Typ Max Unit 13.3 ns 0.5 × t 5.5 ns CLK 0.5 × t 5.5 ns CLK 30.0 ns 0 2.6 ns 1.5 ns 8.5 ns –1.2 +2 ...

Page 4

... DATAn SDI Temp Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full t CLKL IN[17:0 CLK SYNC Test AD6622AS Level Min Typ Max × CLK 2 × × CLK CLK 3 × × CLK CLK 4 × × t ...

Page 5

RD (DS) WR (R/ SAM A[2:0] VALID ADDRESS t SAM VALID DATA D[7:0] t DRDY RDY (DTACK) t ACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM THE THE RE ...

Page 6

AD6622 DS (RD) R/W (WR SAM VALID ADDRESS A[2:0] t SAM VALID DATA D[7:0] DTACK (RDY) ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM THE THE FE OF DTACK. 1. ...

Page 7

... JC Thermal measurements made in the horizontal position on a 2-layer board. Model Temperature Range AD6622AS –40°C to +70°C (Ambient) AD6622S/PCB CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6622 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges ...

Page 8

AD6622 103 GND 104 VDD 105 GND 106 TMS 107 TDO 108 TDI 109 SCLKA 110 VDD 111 SDFSA 112 SDINA SCLKB 113 114 SDFSB GND 115 116 GND 117 GND 118 SDINB 119 SCLKC 120 SDFSC 121 SDINC 122 ...

Page 9

Pin Number Name 1, 3–5, 9, 19–21, 31, 32, GND 34–36, 38, 39, 42, 52–54, 63–65, 68, 69, 72, 73, 83–85, 95, 96, 98, 99, 102, 103, 105, 115–117, 126, 128 2 OEN 27–29, 22–25, 15–18, 10–13, OUT[17:0] 6–8 14, ...

Page 10

AD6622 SDINA SDFSA SCLKA SDINB SDFSB SCLKB SDINC SDFSC SCLKC SDIND SDFSD SCLKD THEORY OF OPERATION As digital-to-analog converters (DACs) achieve higher sampling rates, analog bandwidth, and dynamic range, it becomes increas- ingly attractive to accomplish the first IF stage ...

Page 11

The serial data frame sync output, SDFS, is pulsed high for one SCLK cycle at the input sample rate. The input sample rate is determined by the master clock divided by channel interpolation factor. If the SCLK rate is not ...

Page 12

AD6622 1. Select the Impulse Response Length (N polation Factor (L ). The Impulse Response Length RCF ( limited in three ways: by the available calculation RCF time, by the data memory size (DMEM), and by the coeffi- ...

Page 13

CASCASDED INTEGRATOR COMB (CIC) INTERPOLATING FILTER The I and Q outputs of the RCF stage are interpolated in inte- ger factors by two cascaded integrator comb (CIC) filters. The CIC section is separated into three discrete blocks: a fifth order ...

Page 14

AD6622 Table II lists maximum bandwidth that will be rejected to various levels for CIC5 interpolation factors from 1 to 32. Figure 15 corresponds to the listing in the –110 dB column and the row ...

Page 15

The CIC2 rejects each of the undesired images while passing the image at baseband. The images of a pure tone at channel center (dc) are nulled perfectly, but ...

Page 16

AD6622 PHASE OFFSET 16 16 NCO FREQUENCY WORD NUMERICALLY CONTROLLED OSCILLATOR (NCO) TUNER Each channel has a fully independent tuner. The tuner accepts data from the CIC filter, tunes digital Intermediate Fre- quency ...

Page 17

SUMMATION BLOCK The summation block of the AD6622 serves to combine the out- puts of each channel to create a composite multicarrier signal. The four channels are summed together and the result is then added with the 18-bit wideband input ...

Page 18

AD6622 Start refers to the start- individual channel, chip, or multiple chips channel is not used, it should be put in the Sleep Mode to reduce power dissipation. Following a hard reset (low pulse on the ...

Page 19

... Version Number 000 0010 0111 1000 0000 A BSDL file for this device is available from Analog Devices, Inc. Contact Analog Devices Inc. for more information. AD6622 16 –1). Table VIII. JTAG Pin List Description Test Access Port Reset Test Clock Test Access Port Mode Select ...

Page 20

AD6622 SCALING Proper scaling of the wideband output is critical to maximize the spurious and noise performance of the AD6622. A relatively small overflow anywhere in the data path can cause the spurious free dynamic range to drop precipitously. Scaling ...

Page 21

Microport Control All accesses to the internal registers and memory of the AD6622 are accomplished indirectly through the use of the microproces- sor port external registers shown in Table XII. Accesses to the External Registers are accomplished through the 3-bit ...

Page 22

AD6622 External Address Chan Wrinc Rdinc 6: Addr IA7 IA6 5: Sync Beam 4: Reset Prog D Prog C 3: Byte3 ID31 ID30 2: Byte2 ID23 ID22 1: Byte1 ID15 ID14 0: Byte0 ID7 ID6 External Address ...

Page 23

INTERNAL CONTROL REGISTERS AND ON-CHIP RAM Listed below is the mapping of internal AD6622 registers. Address Bit Width Name Common Function Registers (Not Associated with a Particular Channel) 0x000 8 Summation MODE Control 0x001 8 Sync MODE Control Channel Function ...

Page 24

AD6622 (0x000) Summation Mode Control Controls functions in the summation block of the AD6622. When set high, Bit 0 causes the output data to be clipped (no wrap- around) when overrange of the output occurs. When Bit 0 is low, ...

Page 25

Bit 5 Reserved. Must be set low. Bits 7:6 set the RCF Coarse Scale as shown below. Table XVI. RCF Scaling Bit 7 Bit 6 RCF Coarse Scale – –12 dB ...

Page 26

AD6622 MULTIPLE TSP OPERATION Each of the four Transmit Signal Processors (TSPs) of the AD6622 can adequately reject the interpolation images of nar- row bandwidth carriers such as AMPS, IS-136, GSM, EDGE, and PHS. Wider bandwidth carriers such as IS-95 ...

Page 27

Driving Multiple TSP Serial Ports When properly configured, the AD6622 will drive each SDFS out of phase. Each new piece of data should be driven only into the TSP that pulses its SDFS pin at that time. In the UMTS ...

Page 28

AD6622 0.041 (1.03) 0.031 (0.78) SEATING PLANE 0.003 (0.08) MAX 0.010 (0.25) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 128-Lead MQFP (Metric Quad Flatpack) (S-128A) 0.685 (17.40) 0.669 (17.00) 0.134 (3.40) 0.555 (14.10) MAX 0.547 (13.90) 128 1 TOP ...

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