5962-8946801YA E2V, 5962-8946801YA Datasheet - Page 10

• Manufacturer Part Number: 5962-8946801YA
• Manufacturer: E2V

Specifications of 5962-8946801YA

• Lead Free Status / RoHS Status: Supplier Unconfirmed

DSCC FORM 2234
APR 97
16/ This specification indicates the guaranteed maximum frequency at which a state machine with internal only feedback can
17/ This frequency indicates the maximum frequency at which the device may operate in data path mode (dedicated input pin
18/ This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or
19/ This parameter indicates the minimum time after a synchronous register clock input that the previous register output data
20/ This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register
21/ This specification is a measure of the delay associated with the internal register feedback path for an asynchronous clock
22/ This parameter indicates the guaranteed maximum frequency at which an asynchronously clocked state machine
23/ This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be
24/ This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path
25/ This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with
26/ This parameter indicates the minimum time that the previous register output data is maintained on the output after an
listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD
PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device.
compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a "Q" or "QML" certification
mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used.
approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to
listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-
38535, appendix A and the requirements herein.
with each lot of microcircuits delivered to this drawing.
3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN
3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in
3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an
3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided
3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing.
operate. If register output states must also control external points, this frequency can still be observed as long as this
frequency is less than 1/t
to output pin). This assumes data input signals are applied to dedicated input pins and no expander logic is used. If any
of the data inputs are I/O pins, t
buried register can be cycled by a clock signal applied to the dedicated clock input pin.
is maintained on the output pin.
output signal to the input of the LAB logic array and then to a combinatorial output. This delay assumes no expanders are
used in logic of combinatorial output or the asynchronous clock input. The clock signal is applied to the dedicated clock
input pin and all feedback is within a single LAB.
to LAB logic array input. This delay plus the asynchronous register setup time, t
internal asynchronously clocked state machine configuration. This delay is for feedback within the same LAB, assumes no
expander logic in the clock path and assumes that the clock input signal is applied to a dedicated input pin.
configuration with external feedback can operate. It is assumed that all data inputs, clock inputs, and feedback signals are
applied to dedicated inputs and that no expander logic is employed in the clock signal path or data path.
cycled in asynchronously clocked mode by a clock signal applied to an external dedicated input pin.
mode. This specification is determined by the least of 1/(t
input signals are applied to dedicated input pins and no expander logic is used.
internal only feedback can operate. This parameter is determined by the lesser of (1/(t
register output states must also control external points, this frequency can still be observed as long as this frequency is
less than 1/t
asynchronous register clock input applied to an external dedicated input pin.
This specification assumes no expander logic is utilized, all data inputs and clock inputs are applied to dedicated inputs,
and all state feedback is within a single LAB.
DEFENSE SUPPLY CENTER COLUMBUS
MICROCIRCUIT DRAWING
COLUMBUS, OHIO 43218-3990
ACO1
.
STANDARD
CO1
.
TABLE I. Electrical performance characteristics - Continued.
S2
is the appropriate t
S
for calculation.
AWH
+ t
AWL
SIZE
A
), 1/(t
AS1
+ t
REVISION LEVEL
AH
AS1
) or 1/(t
, is the minimum internal period for an
ACF
ACO1
C
+ t
AS
). It assumes data and clock
)) or (1/(t
AWH
SHEET
+ t
5962-89468
AWL
)). If
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