MC9328MXLVP15R2 Freescale, MC9328MXLVP15R2 Datasheet

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... MAPBGA package. Figure 1 shows the functional block diagram of the i.MXL processor. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2004, 2005, 2006. All rights reserved. Document Number: MC9328MXL Rev ...

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... I Cache D Cache Interrupt AIPI 1 VMMU Controller DMAC Bus AIPI 2 (11 Chnl) Control EIM & SDRAMC 2 S) Module MC9328MXL Technical Data, Rev. 8 Standard System I/O GPIO PWM Timer 1 & 2 RTC Watchdog Multimedia Multimedia Accelerator Video Port Human Interface LCD Controller Freescale Semiconductor ...

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... Logic level zero is a voltage that corresponds to Boolean false (0) state. • To set a bit or bits means to establish logic level one. • To clear a bit or bits means to establish logic level zero. • A signal is an electronic construct whose state conveys or changes in state convey information. Freescale Semiconductor Table 1. i.MXL Ordering Information Temperature Solderball Type ...

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... DTACK as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the external DTACK signal after 1022 clock counts have elapsed. 4 Table 2. i.MXL Signal Descriptions Function/Notes External Bus/Chip-Select (EIM) MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor ...

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... Power-on reset, External reset (RESET_IN), and Watchdog time-out. POR Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally generated by an external RC circuit designed to detect a power-up event. Freescale Semiconductor Function/Notes Bootstrap SDRAM Controller Clocks and Resets MC9328MXL Technical Data, Rev ...

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... This signal is used to control the LCD bias voltage as contrast control. SPL_SPR Program horizontal scan direction (Sharp panel dedicated signal). PS Control signal output for source driver (Sharp panel dedicated signal). 6 Function/Notes JTAG DMA ETM CMOS Sensor Interface LCD Controller MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor ...

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... SD_CMD SD Command—If the system designer does not wish to make use of the internal pull-up, via the Pull-up enable register, a 4.7K–69K external pull up resistor must be added. SD_CLK MMC Output Clock Freescale Semiconductor Function/Notes SPI 1 and SPI 2 General Purpose Timers USB Device Secure Digital Interface MC9328MXL Technical Data, Rev ...

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... Transmit Data SSI_RXDAT Receive Data SSI_TXCLK Transmit Serial Clock SSI_RXCLK Receive Serial Clock SSI_TXFS Transmit Frame Sync SSI_RXFS Receive Frame Sync 2 I2C_SCL I C Clock 2 I2C_SDA I C Data 8 Function/Notes Memory Stick Interface UARTs – IrDA/Auto-Bauding 2 S protocol MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor ...

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... NVDD1 E4 D3 D29 NVDD1 E1 E2 A21 NVDD1 F3 E3 D28 Freescale Semiconductor Function/Notes PWM Test Function ® registered trademark of National Semiconductor.) Digital Supply Pins Supply Pins – Analog Modules Internal Power Supply Table 6 allows the user to select the function of each pin by Primary ...

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... I/O 69K O I/O 69K O I/O 69K O I/O 69K O I/O 69K O I/O 69K O I/O 69K O I/O 69K O I/O 69K O I/O 69K MC9328MXL Technical Data, Rev. 8 AIN BIN AOUT Default Pull -Up 69K A20 69K A19 69K A18 69K A17 69K A16 Freescale Semiconductor ...

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... N9 N7 PA17 NVDD1 K10 N8 D1 NVDD1 M10 M7 RW NVDD1 P10 T8 MA11 NVDD1 P9 M8 MA10 NVDD1 N10 R9 D0 NVDD1 R12 P9 DQM3 Freescale Semiconductor Primary Alternate GPIO Pull- Dir Signal Dir Mux Up O I/O 69K O O I/O 69K I/O 69K PA23 I/O 69K ...

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... NVDD2 J11 P14 I2C_SCL NVDD2 H14 P15 I2C_SDA 12 Primary Alternate GPIO Pull- Dir Signal Dir Mux Static Static I 69K 69K 69K I 69K I 69K O PA16 I/O PA15 MC9328MXL Technical Data, Rev. 8 AIN BIN AOUT Default Pull -Up 69K PA16 69K PA15 Freescale Semiconductor ...

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... A14 H13 LD4 NVDD2 B13 H16 LD3 NVDD2 A13 H12 LD2 NVDD2 D12 G16 LD1 NVDD2 B12 H11 LD0 NVDD2 C11 G15 FLM/VSY NC Freescale Semiconductor Primary Alternate GPIO Pull- Dir Signal Dir Mux Up I PA14 I PA13 I PA12 I PA11 I PA10 I PA9 I PA8 ...

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... SPI2_ PD7 SCLK 69K PD6 69K PC17 69K PC16 69K PC15 69K PC14 69K PC13 DMA_REQ 69K PC12 69K PC11 69K PC10 69K PC9 69K PC8 69K PC7 69K PC6 69K PC5 69K PC4 69K PC3 69K PB31 Freescale Semiconductor ...

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... D3 B2 SD_DAT1 NVDD4 C2 C3 SD_DAT0 NVDD1 D5 K8 NVDD1 G6 A1 NVSS NVDD1 E5 H5 NVDD1 H6 T1 NVSS QVDD1 J8 H9 QVDD1 E6 H8 QVSS Freescale Semiconductor Primary Alternate GPIO Pull- Dir Signal Dir Mux Up O PB30 I PB29 O PB28 O PB27 O PB26 I PB25 I PB24 O PB23 I/O PB22 ...

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... Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static MC9328MXL Technical Data, Rev. 8 AIN BIN AOUT Default Pull -Up Freescale Semiconductor ...

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... Because AVDD pins are supply voltages to the analog pads recommended to isolate and noise-filter the AVDD pins from other VDD pins. For more information about I/O pads grouping per VDD, please refer to Freescale Semiconductor Table 4. Maximum Ratings Rating Minimum MC9328MXL Technical Data, Rev ...

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... MC9328MXL Technical Data, Rev. 8 Minimum Maximum Unit 0 70 °C -30 70 °C -40 85 °C 2.70 3.30 V 1.70 3.30 V 1.70 1.90 V 1.80 2.00 V 1.70 3.30 V Typical Max Unit QVDD at – mA 1.8V = 120mA; NVDD+AVDD at 3.0V = 30mA μA 25 – μA 45 – μA 35 – μA 60 – Freescale Semiconductor ...

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... Table 8. 32k/16M Oscillator Signal Timing Parameter EXTAL32k input jitter (peak to peak) EXTAL32k startup time EXTAL16M input jitter (peak to peak) 1 EXTAL16M startup time 1 The 16 MHz oscillator is not recommended for use in new designs. Freescale Semiconductor Min 0.7V = 2.0 mA) 0.7V 4.0 -4 under an operating temperature from T DD max Table 7 ...

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... ETM9 timing parameters used Valid Data 4a Figure 2. Trace Port Timing Diagram 1.8 ± 0.1 V Minimum Maximum Minimum 0 85 1.3 – 3 – – 4 – 3 MC9328MXL Technical Data, Rev Valid Data 4b 3.0 ± 0.3 V Unit Maximum 0 100 MHz 2 – – ns – – Freescale Semiconductor ...

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... Freq jitter (p-p) – Phase jitter (p-p) Integer MF, FPL mode, Vcc=1.8V Power supply voltage – Power dissipation FOL mode, integer MF 200 MHz, Vcc = 1.8V dck Freescale Semiconductor Functional Description and Application Information 1.8 ± 0.1 V Minimum Maximum Minimum 2.28 – 3.42 – Table 10 ...

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... RESET_DRAM HRESET RESET_OUT CLK32 HCLK Figure 3. Timing Relationship with POR RESET_IN HRESET RESET_OUT 6 CLK32 HCLK Figure 4. Timing Relationship with RESET_IN 22 NOTE 1 10% AVDD 2 Exact 300ms 3 5 MC9328MXL Technical Data, Rev. 8 Figure 3 and 7 cycles @ CLK32 4 14 cycles @ CLK32 14 cycles @ CLK32 4 Freescale Semiconductor ...

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... The External Interface Module (EIM) handles the interface to devices external to the i.MXL processor, including the generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown in Figure 5, and Table 12 Freescale Semiconductor Functional Description and Application Information 1.8 ± 0.1 V Min Max 1 ...

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... MC9328MXL Technical Data, Rev 10a 3.0 ± 0.3 V Unit Min Typical Max 2.4 3.2 8.8 ns 1.5 2.4 5.5 ns 2.6 3.2 7.6 ns 1.5 2.4 6.1 ns 1.3 2.7 6.3 ns 1.8 2.5 5.9 ns Freescale Semiconductor ...

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... DTACK Signal Timing Figure 6 through Figure 9 show the access cycle timing used by chip-select 5. The signal values and units of measure for this figure are found in the associated tables. Freescale Semiconductor Functional Description and Application Information 1.8 ± 0.1 V Min Typical Max 2.32 2 ...

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... The external wait input requirement is eliminated when CS5 is programmed to use internal wait state 3.0 ± 0.3 V Minimum See note 2 3T 56.81 – 2T+1.57 T-1.49 0 1.5T-0.68 0. MC9328MXL Technical Data, Rev Unit Maximum – ns – ns 57.28 ns 1020T ns 3T+7.33 ns – 1.5T-0.06 ns 0.18 ns 1019T ns 1020T ns Freescale Semiconductor ...

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... Wait asserted to OE negated 7 Data hold timing after OE negated 8 Data ready after wait is asserted 9 CS deactive to next CS active 10 OE negate after EB negate 11 Wait becomes low after CS5 asserted Freescale Semiconductor Functional Description and Application Information Minimum See note 2 3T 1.5T-0.68 – ...

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... RW negated to Address inactive 6 Wait asserted after CS5 asserted 28 Minimum Minimum See note 2 See note 2 3T 2.5T-3.63 64.22 – MC9328MXL Technical Data, Rev. 8 3.0 ± 0.3 V Unit Maximum 1020T 3.0 ± 0.3 V Unit Maximum – ns – ns – ns 2.5T-1.16 ns – ns 1020T ns Freescale Semiconductor ...

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... WAIT Write Cycle DMA Enabled Address 1 programmable min 0ns CS5 2 programmable min 0ns (logic high) 12 WAIT 9 DATABUS Figure 9. WAIT Write Cycle DMA Enabled Freescale Semiconductor Functional Description and Application Information 3.0 ± 0.3 V Minimum T+2.66 2T+0.03 – 0. MC9328MXL Technical Data, Rev. 8 Unit Maximum 2T+7.96 ns – ...

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... V Minimum See note 2 See note 2 3T 2.5T-3.63 – – T+2.66 2T+0.03 – MC9328MXL Technical Data, Rev. 8 Unit Maximum – ns – ns – ns 2.5T-1.16 ns 0.09 ns 1020T ns 2T+7.96 ns – – ns 0.5T+0.5 1019T ns 1020T ns , including i.MXL Freescale Semiconductor ...

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... CS2 R/W LBA EBx (EBC = EBx (EBC =1) DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Freescale Semiconductor Functional Description and Application Information Read V1 Last Valid Data Read Figure 10. WSC = 1, A.HALF/E.HALF MC9328MXL Technical Data, Rev ...

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... Last Valid Data weim_hrdata weim_hready BCLK (burst clock) Last Valid Address ADDR CS0 R/W LBA OE EB DATA Figure 11. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF 32 V1 Write Data (V1) Last Valid Data Write Last Valid Data MC9328MXL Technical Data, Rev. 8 Unknown V1 Write Data (V1) Freescale Semiconductor ...

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... EBx (EBC =1) DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 12. WSC = 1, OEA = 1, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Address V1 Read 1/2 Half Word MC9328MXL Technical Data, Rev Word Address 2/2 Half Word ...

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... Last Valid Data weim_hrdata weim_hready BCLK (burst clock) ADDR Last Valid Addr CS0 R/W LBA OE EB DATA Figure 13. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF 34 Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MXL Technical Data, Rev. 8 Address 2/2 Half Word Freescale Semiconductor ...

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... EBx (EBC =1) DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 14. WSC = 3, OEA = 2, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Last Valid Data Address V1 Read 1/2 Half Word MC9328MXL Technical Data, Rev Word ...

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... BCLK (burst clock) ADDR Last Valid Addr CS3 R/W LBA OE EB DATA Last Valid Data Figure 15. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF 36 Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MXL Technical Data, Rev. 8 Address 2/2 Half Word Freescale Semiconductor ...

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... EBx (EBC =1) weim_data_in Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 16. WSC = 3, OEA = 4, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Last Valid Data Address V1 Read 1/2 Half Word MC9328MXL Technical Data, Rev Word ...

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... BCLK (burst clock) ADDR Last Valid Addr CS2 R/W LBA OE EB DATA Last Valid Data Figure 17. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF 38 Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MXL Technical Data, Rev. 8 Address 2/2 Half Word Freescale Semiconductor ...

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... EBx (EBC =1) DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 18. WSC = 3, OEN = 2, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Last Valid Data Address V1 Read 1/2 Half Word MC9328MXL Technical Data, Rev Word ...

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... EBx (EBC =1) DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 19. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF 40 Last Valid Data Address V1 Read 1/2 Half Word MC9328MXL Technical Data, Rev Word Address 2/2 Half Word Freescale Semiconductor ...

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... Last Valid Addr CS2 R/W LBA OE EB DATA Last Valid Data Figure 20. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MXL Technical Data, Rev. 8 Unknown Address ...

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... BCLK (burst clock) ADDR Last Valid Addr CS2 R/W LBA OE EB DATA Last Valid Data Figure 21. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF 42 Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MXL Technical Data, Rev. 8 Unknown Address 2/2 Half Word Freescale Semiconductor ...

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... EBx (EBC =1) DATA DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 22. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF Freescale Semiconductor Functional Description and Application Information Nonseq Write V8 Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MXL Technical Data, Rev ...

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... Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 23. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF 44 Read Idle Nonseq Write V8 Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MXL Technical Data, Rev. 8 Write Write Data Read Data Address V8 Write Write Data Freescale Semiconductor ...

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... Last Valid Addr CS R/W LBA OE EB DATA Last Valid Data Figure 24. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Write Data (Word) Last Valid Data Address V1 Write Write Data (1/2 Half Word) MC9328MXL Technical Data, Rev. 8 Address Write Data (2/2 Half Word) ...

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... Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 25. WSC = 3, CSA = 1, A.HALF/E.HALF 46 Nonseq Write V8 Last Valid Data Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MXL Technical Data, Rev. 8 Write Data Read Data Address V8 Write Write Data Freescale Semiconductor ...

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... EBx (EBC =1) DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 26. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF Freescale Semiconductor Functional Description and Application Information Idle Seq Read V2 Read Data (V1) Address V1 CNC Read Read Data (V1) MC9328MXL Technical Data, Rev ...

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... Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 27. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF 48 Idle Nonseq Write V8 Last Valid Data Read Data Address V1 CNC Read Read Data Last Valid Data MC9328MXL Technical Data, Rev. 8 Write Data Address V8 Write Write Data Freescale Semiconductor ...

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... EBx (EBC =1) ECB DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 28. WSC = 3, SYNC = 1, A.HALF/E.HALF Freescale Semiconductor Functional Description and Application Information Nonse Read V5 Address V1 Read V1 Word V2 Word MC9328MXL Technical Data, Rev. 8 Idle ...

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... Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 29. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD 50 Seq Seq Read Read Word V2 Word Address V1 Read V1 Word V2 Word V3 Word MC9328MXL Technical Data, Rev. 8 Idle Seq Read V4 V3 Word V4 Word V4 Word Freescale Semiconductor ...

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... EBx (EBC =1) ECB DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 30. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Seq Read V2 V1 Word Address V1 Read V1 1/2 V1 2/2 MC9328MXL Technical Data, Rev. 8 ...

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... Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 31. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF 52 Seq Read Last Valid Data Address V1 Read V1 1/2 V1 2/2 MC9328MXL Technical Data, Rev. 8 Idle V2 V1 Word V2 Word V2 1/2 V2 2/2 Freescale Semiconductor ...

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... EBx (EBC =1) ECB DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 32. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Seq Read Last Valid Data Address V1 Read V1 1/2 V1 2/2 MC9328MXL Technical Data, Rev ...

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... T1 T3 XMAX Ts Figure 33. Non-TFT Panel Timing Allowed Register 1, 2 Minimum Value – 0 through Figure 38 show the timing relationship of the master SPI using MC9328MXL Technical Data, Rev Actual Value Unit HWAIT2+2 4 Tpix HWIDTH+1 Tpix 0 ≤ T3 ≤ – HWAIT1+1 Tpix Freescale Semiconductor ...

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... Figure 36. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger SS (input) SCLK, MOSI, MISO Figure 37. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT SS (input) 6 SCLK, MOSI, MISO Figure 38. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge Freescale Semiconductor Functional Description and Application Information MC9328MXL Technical Data, Rev. 8 ...

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... Tsclk 2 • Tsclk 0 Tsclk + WAIT Figure 39. SPI SCLK Timing Diagram Parameter Minimum 0 100 1 MC9328MXL Technical Data, Rev. 8 Figure 38 3.0 ± 0.3 V Unit Maximum 1 – – ns – ns – ns – – ns – ns 3.0 ± 0.3 V Unit Maximum 10 MHz – ns Freescale Semiconductor ...

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... Symbol Description T1 End beginning of VSYN T2 HSYN period T3 VSYN pulse width T4 End of VSYN to beginning HSYN pulse width T6 End of HSYN to beginning End beginning of HSYN Freescale Semiconductor Functional Description and Application Information 3.0 ± 0.3 V Minimum – Non-display XMAX T8 (1,1) (1,2) (1,X) T9 T10 Minimum ...

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... MMC/SD module (inner system) and the application (user programming). Bus Clock CMD_DAT Input CMD_DAT Output Figure 42. Chip-Select Read Cycle Timing Diagram 58 Minimum Corresponding Register Value - Valid Data 7 Valid Data 6a MC9328MXL Technical Data, Rev. 8 Unit Figure 41, all 3 signals 4b 5b Valid Data Valid Data 6b Freescale Semiconductor ...

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... Table 23. Table 23. State Signal Parameters for Card Active Symbol Definition Z High impedance state D Data bits * Repetition CRC Cyclic redundancy check bits (7 bits) Freescale Semiconductor Functional Description and Application Information 1.8 ± 0.1 V Minimum Maximum 0 25 400 6/33 – 15/75 – – ...

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... CRC E Z ****** Content Timing response end to next CMD start (data transfer mode) N cycles CC Host Command CRC ****** Content Timing of command sequences (all modes) until the card sees a stop transmission command. The AC MC9328MXL Technical Data, Rev and CRC CRC CRC beginning AC Freescale Semiconductor ...

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... CRC status (101); otherwise, a positive CRC status (010) is returned. The card expects a continuous flow of data blocks configured to multiple block mode, with the flow terminated by a stop transmission command. Freescale Semiconductor Functional Description and Application Information N ...

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... Functional Description and Application Information Figure 46. Timing Diagrams at Data Write The stop transmission command may occur when the card is in different states. different scenarios on the bus. 62 MC9328MXL Technical Data, Rev. 8 Figure 47 shows the Freescale Semiconductor ...

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... Figure 47. Stop Transmission During Different Scenarios Table 24. Timing Values for Parameter MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL) Command response cycle Identification response cycle Access time delay cycle Freescale Semiconductor Functional Description and Application Information Figure 43 through Symbol Minimum NCR ...

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... Minimum NRC 8 NCC 8 NWR 2 NST 2 S Response IRQ Block Data Interrupt Period Figure 48. SDIO IRQ Timing Diagram MC9328MXL Technical Data, Rev. 8 (Continued) Maximum Unit – Clock cycles – Clock cycles – Clock cycles 2 Clock cycles ****** IRQ Block Data S E Freescale Semiconductor ...

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... The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When an error occurs during packet communication, the mode is shifted to two-state access mode, and the BS0 and BS1 bus states are automatically repeated to avoid a bus collision on the SDIO. Freescale Semiconductor Functional Description and Application Information ...

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... MS_SCLKO low pulse width 1 9 MS_SCLKO rise time 1 10 MS_SCLKO fall time 1 11 MS_BS delay time Parameter 1 1 MC9328MXL Technical Data, Rev 3.0 ± 0.3 V Unit Minimum Maximum – 25 MHz 20 – – ns – – – 25 MHz 20 – – ns – – – Freescale Semiconductor ...

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... Figure 51. PWM Output Timing Diagram Table 26. PWM Output Timing Parameter Table Ref No. Parameter 1 1 System CLK frequency 1 2a Clock high time 1 2b Clock low time 1 3a Clock fall time Freescale Semiconductor Functional Description and Application Information Parameter 1 Table 26 1.8 ± 0.1 V Minimum ...

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... Figure 52. SDRAM Read Cycle Timing Diagram 68 1.8 ± 0.1 V Minimum Maximum Minimum – 6.67 5.7 – 5.7 – COL/ Data Note: CKE is high during the read/write cycle. MC9328MXL Technical Data, Rev. 8 3.0 ± 0.3 V Unit Maximum – 5/ – – Freescale Semiconductor ...

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... Data out high-impedance time ( Data out high-impedance time ( Active to read/write command period ( SDRAM clock cycle time. This settings can be found in the MC9328MXL reference manual. RCD Freescale Semiconductor Functional Description and Application Information 1.8 ± 0.1 V Minimum Maximum 2.67 – 6 – 11.4 – ...

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... RP t – RCD2 4.0 – 2.28 – MC9328MXL Technical Data, Rev. 8 COL/BA 9 DATA 3.0 ± 0.3 V Unit Minimum Maximum 4 – – – – – – ns RP2 t – ns RCD2 2 – – ns Freescale Semiconductor ...

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... Address setup time 5 Address hold time 6 Precharge cycle period 7 Auto precharge command period 1 t and t = SDRAM clock cycle time. These settings can be found in the MC9328MXL reference manual Freescale Semiconductor Functional Description and Application Information 1.8 ± 0.1 V Minimum Maximum 2.67 – 6 – 11.4 – ...

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... Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same packet transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved in the form of packets, however, because isochronous pipes are given a fixed portion of the USB bandwidth at all times, there is no end-of-transfer. 72 MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor ...

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... ROE_VMO USBD_VPO high to USBD_ROE deactivated VPO_ROE USBD_VMO low to USBD_ROE deactivated (includes SE0) VMO_ROE SE0 interval of EOP FEOPT Data transfer rate PERIOD Freescale Semiconductor Functional Description and Application Information 6 t PERIOD 2 MC9328MXL Technical Data, Rev VMO_ROE 3 t VPO_ROE t FEOPT 5 3.0 ± 0.3 V ...

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... The I C communication protocol consists of seven elements: START, Data Source/Recipient, Data Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP. SDA SCL Figure 58. Definition of Bus Timing for I 74 Parameter Minimum MC9328MXL Technical Data, Rev FEOPR 3.0 ± 0.3 V Unit Maximum – Freescale Semiconductor ...

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... STCK Output STFS (bl) Output STFS (wl) Output STXD Output SRXD Input Note: SRXD input in synchronous mode only. Figure 59. SSI Transmitter Internal Clock Timing Diagram Freescale Semiconductor Functional Description and Application Information 2 C Bus Timing Parameter Table 1.8 ± 0.1 V Minimum Maximum 182 – ...

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... SRFS (bl) Output SRFS (wl) Output SRXD Input Figure 60. SSI Receiver Internal Clock Timing Diagram STCK Input STFS (bl) Input STFS (wl) Input STXD Output SRXD Input Note: SRXD Input in Synchronous mode only Figure 61. SSI Transmitter External Clock Timing Diagram MC9328MXL Technical Data, Rev Freescale Semiconductor ...

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... SRXD setup time before SRCK low 14 SRXD hold time after SRCK low External Clock Operation (Port C Primary Function 1 15 STCK/SRCK clock period 16 STCK/SRCK clock high period 17 STCK/SRCK clock low period Freescale Semiconductor Functional Description and Application Information 1.8 ± 0.1 V Minimum ...

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... Freescale Semiconductor ...

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... STCK high to STFS (wl) low 3 25 SRCK high to SRFS (wl) low 26 STCK high to STXD valid from high impedance 27a STCK high to STXD high 27b STCK high to STXD low Freescale Semiconductor Functional Description and Application Information 1.8 ± 0.1 V Minimum Maximum 1 (Port B Alternate Function 95 – ...

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... Maximum 17.90 29.75 1.14 – 0 – 18.81 – 0 – 1.14 – 0 – Figure 64 MC9328MXL Technical Data, Rev. 8 3.0 ± 0.3 V Unit Minimum Maximum 15.7 26.1 ns 1.0 – – 16.5 – – 1.0 – – ns shows the timing diagram Table 35. Freescale Semiconductor ...

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... Table 35. Gated Clock Mode Timing Parameters Ref No. 1 csi_vsync to csi_hsync 2 csi_hsync to csi_pixclk 3 csi_d setup time 4 csi_d hold time 5 csi_pixclk high time 6 csi_pixclk low time 7 csi_pixclk frequency Freescale Semiconductor Functional Description and Application Information 5 2 Valid Data Valid Data Valid Data Valid Data 3 4 Parameter ...

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... The parameters for the timing diagrams are listed in VSYNC PIXCLK DATA[7:0] Figure 65. Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge 82 Figure Valid Data Valid Data 2 3 MC9328MXL Technical Data, Rev. 8 shows the timing diagram Table 36 Valid Data Freescale Semiconductor ...

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... Falling-edge latch data max fall time allowed = (negative duty cycle - hold time) max rise time allowed = (positive duty cycle - setup time) Freescale Semiconductor Functional Description and Application Information 1 5 Valid Data Valid Data ...

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... Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MXL Product Family 5 Pin-Out and Package Information Table 37 illustrates the package pin assignments for the 256-pin MAPBGA package ...

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... Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MXL Product Family Table 38 illustrates the package pin assignments for the 225-contact MAPBGA package. For a complete listing of signals, see the Signal Multiplexing Table 3 on page 9 ...

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... DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994. 3.MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS. Figure 67. i.MXL 256 MAPBGA Mechanical Drawing 86 Case Outline 1367 MC9328MXL Technical Data, Rev. 8 SIDE VIEW Freescale Semiconductor ...

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... DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS. 5.PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE Figure 68. i.MXL 225 MAPBGA Mechanical Drawing Freescale Semiconductor Case Outline 1304B MC9328MXL Technical Data, Rev. 8 Pin-Out and Package Information SIDE VIEW ...

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... MC9328MXL Product Brief (order number MC9328MXLP) MC9328MXL Reference Manual (order number MC9328MXLRM) The Freescale manuals are available on the Freescale Semiconductors Web site at http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web site, or printed versions may be ordered. The ARM Ltd. documentation is available from http://www ...

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... Freescale Semiconductor NOTES MC9328MXL Technical Data, Rev ...

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... Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use ...