TS68882MF1B/C20 E2V, TS68882MF1B/C20 Datasheet - Page 31

• Manufacturer Part Number: TS68882MF1B/C20
• Manufacturer: E2V

Specifications of TS68882MF1B/C20

• Operating Temperature (max): 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

8.16
8.17
e2v semiconductors SAS 2007
Addressing Modes
Address Bus (A0 through A4)
The TS68882 does not perform address calculations. This satisfies the criterion that a TS68000 Family
co-processor must not depend on certain features or capabilities that may or may not be implemented by
a given main processor. Thus, when the TS68882 instructs the TS68020/TS68030 to transfer an oper-
and via the co-processor interface, the MPU performs the addressing mode calculations requested in the
instruction. In this case, the instruction is encoded specifically for the TS68020/TS68030, and the execu-
tion of the TS68882 is not dependent on that encoding, but only on the value of the command word
written to the TS68882 by the main processor.
This interface is quite flexible and allows any addressing mode to be used with floating-point instructions.
For the TS68000 Family, these addressing modes include immediate, postincrement, predecrement,
data or address register direct, and the indexed/indirect addressing modes of the TS68020/TS68030.
Some addressing modes are restricted for some instructions in keeping with the TS68000 Family archi-
tectural definitions (i.e., PC relative addressing is not allowed for a destination operand).
The orthogonal instruction set of the TS68882, along with the flexible branches and addressing modes,
allows a programmer writing assembly language code, or a compiler writer generating object or source
code for the MPU/TS68882 device pair, to think of the TS68882 as though it is part of the MPU. There
are no special restrictions imposed by the co-processor interface, and floating-point arithmetic is coded
exactly like integer arithmetic.
These active-high address line inputs are used by the main processor to select the co-processor inter-
face register locations located in the CPU address space. These lines control the register selection as
listed in
When the TS68882 is configured to operate over an 8-bit data bus, the A0 pin is used as an address sig-
nal for byte accesses of the co-processor interface registers. When the TS68882 is configured to
operate over a 16- or 32-bit system data bus, both the A0 and SIZE pins are strapped high and/or low as
listed in
Table 8-3.
A4-A0
0000x
0001x
0010x
0011x
0100x
0101x
0110x
0111x
1010x
100xx
Table
Table
8-3.
8-4.
Co-processor Interface Register Selection
Offset
S0A
S0C
S0E
S00
S02
S04
S06
S08
S10
S14
Width
16
16
16
16
16
16
16
16
32
16
Read
Read
Read
Type
Write
Write
Write
R/W
R/W
-
-
0852B–HIREL–06/07
Register
Response
Control
Save
Restore
(Reserved)
Command
(Reserved)
Condition
Operand
Register select
TS68882
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