DSP56303VF100 Freescale, DSP56303VF100 Datasheet - Page 40

• Manufacturer Part Number: DSP56303VF100
• Manufacturer: Freescale

Specifications of DSP56303VF100

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Specifications
2-20
Notes:
No.
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
RAS assertion to row address not valid
Column address valid to CAS assertion
CAS assertion to column address not valid
RAS assertion to column address not valid
Column address valid to RAS deassertion
WR deassertion to CAS assertion
CAS deassertion to WR
RAS deassertion to WR
CAS assertion to WR deassertion
RAS assertion to WR deassertion
WR assertion pulse width
WR assertion to RAS deassertion
WR assertion to CAS deassertion
Data valid to CAS assertion (write)
CAS assertion to data not valid (write)
RAS assertion to data not valid (write)
WR assertion to CAS assertion
CAS assertion to RAS assertion (refresh)
RAS deassertion to CAS assertion (refresh)
RD assertion to RAS deassertion
RD assertion to data valid
RD deassertion to data not valid
WR assertion to data active
WR deassertion to data high impedance
1.
2.
3.
4.
5.
Table 2-11.
The number of wait states for an out-of-page access is specified in the DRAM Control Register.
The refresh period is specified in the DRAM Control Register.
Use the expression to compute the maximum or minimum value listed (or both if the expression includes ±) .
Either t
RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t
RCH
or t
RRH
DRAM Out-of-Page and Refresh Timings, Eleven Wait States
4
4
Characteristics
assertion
assertion
must be satisfied for read cycles.
5
DSP56303 Technical Data, Rev. 11
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WCH
WCR
t
WCS
RAH
CAH
t
RCS
RCH
RRH
RWL
CWL
t
t
DHR
CSR
RPC
ROH
t
t
ASC
RAL
WP
AR
DS
DH
GA
GZ
11.75 × T
10.25 × T
1.75 × T
0.75 × T
Expression
1.75 × T
0.75 × T
5.25 × T
7.75 × T
0.25 × T
11.5 × T
5.75 × T
5.25 × T
7.75 × T
2.75 × T
11.5 × T
3.0 × T
7.5 × T
6.5 × T
1.5 × T
10 × T
6 × T
5 × T
0.25 × T
C
C
C
C
C
C
C
C
C
OFF
C
C
C
C
C
C
C
C
C
C
C
− 4.0
− 4.2
C
C
− 7.0
− 4.0
− 4.2
− 4.3
− 4.0
– 1.5
− 4.0
− 4.0
− 4.0
− 4.0
– 3.7
− 2.0
− 4.5
− 4.0
− 4.0
− 4.0
− 4.0
− 4.0
− 4.3
− 4.3
C
and not t
1,2
3
Freescale Semiconductor
(Continued)
GZ
110.5
113.2
111.0
Min
13.5
48.5
73.5
56.0
26.0
13.8
45.8
70.8
98.2
53.5
48.5
73.5
60.7
11.0
23.5
3.5
0.5
0.0
6.0
—
—
.
100 MHz
Max
93.0
2.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns