CY8C5246AXI-038 Cypress Semiconductor Corp, CY8C5246AXI-038 Datasheet
CY8C5246AXI-038
Specifications of CY8C5246AXI-038
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CY8C5246AXI-038 Summary of contents
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... Library of standard peripherals Notes 1. This feature on select devices only. See Ordering Information 2. GPIOs with opamp outputs are not recommended for use with CapSense. Cypress Semiconductor Corporation Document Number: 001-55034 Rev. *G PRELIMINARY ® PSoC 5: CY8C52 Family Datasheet Programmable System-on-Chip (PSoC ® ...
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Contents 1. Architectural Overview ................................................ 3 2. Pinouts .......................................................................... 5 3. Pin Descriptions ........................................................... 9 4. CPU ................................................................................ 9 4.1 ARM Cortex-M3 CPU ............................................ 9 4.1 Cache Controller ................................................. 11 4.2 DMA and PHUB .................................................. 11 4.3 Interrupt Controller .............................................. ...
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Architectural Overview Introducing the CY8C52 family of ultra low power, flash Programmable System-on-Chip (PSoC) devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C52 family provides configurable blocks of analog, digital, and interconnect circuitry ...
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CY8C52 family these blocks can include four 16-bit timers, 2 counters, and PWM blocks slave, master, and multimaster; Full-Speed USB; and Full CAN 2.0b. For more details on the peripherals see the Peripherals” section on page 30 of ...
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The details of the PSoC power modes are covered in the System” section on page 20 of this datasheet. PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for programming, debug, and test. Using these standard interfaces enables the designer to ...
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GPIO) P2[6] (TRACEDATA[3], GPIO) P2[7] (I2C0: SCL, SIO) P12[4] (I2C0: SDA, SIO) P12[5] Vboost XRES (TMS, SWDIO, GPIO) P1[0] (TCK, SWDCK, GPIO) P1[1] (configurable XRES, GPIO) P1[2] (TDO, SWV, GPIO) P1[3] (TDI, GPIO) P1[4] (nTRST, GPIO) P1[5] Vddio1 Notes ...
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GPIO) P2[5] 1 (TRACEDATA[2], GPIO) P2[6] 2 (TRACEDATA[3], GPIO) P2[7] 3 (I2C0: SCL, SIO) P12[4] 4 (I2C0: SDA, SIO) P12[5] 5 (GPIO) P6[4] 6 (GPIO) P6[5] 7 (GPIO) P6[6] 8 (GPIO) P6[7] 9 Vssb 10 Ind 11 Vboost 12 ...
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Figure 2-4. Example Schematic for 100-pin TQFP Part with Power Connections Vddd C6 0.1 uF Vssd 1 P2[5] 2 P2[6] 3 P2[7] 4 P12[4], SIO 5 P12[5], SIO 6 P6[4] 7 P6[5] 8 P6[6] 9 P6[7] 10 Vssb 11 Ind ...
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Pin Descriptions IDAC0. Low resistance output pin for high IDAC. Extref0, Extref1. External reference input to the analog system. GPIO. General purpose I/O pin provides interfaces to the CPU, digital peripherals, analog peripherals, interrupts, LCD segment [7] drive, and ...
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Nested Interrupt Inputs Vectored Interrupt Controller (NVIC) Debug Block JTAG/SWD (Serial and JTAG Bus SRAM Matrix 32 KB Bus SRAM Matrix AHB Spokes GPIO & EMIF The Cortex-M3 CPU subsystem includes these features: ARM Cortex-M3 CPU Programmable ...
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Because the handler mode is only enabled at the privileged level, there are actually only three states, as shown in Table 4-1. Operational Level Condition Privileged Running an exception Handler mode Running main program Thread mode At the user level, ...
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PHUB Features CPU and DMA controller are both bus masters to the PHUB Eight multi-layer AHB bus parallel access paths (spokes) for peripheral access Simultaneous CPU and DMA access to peripherals located on different spokes Simultaneous ...
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TD that reads the target address location from the peripheral and writes that value into a subsequent TD in the chain. This modifies the TD chain on the fly. When the “address fetch” TD completes it moves on ...
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Dynamic reprioritization of interrupts. Priority grouping. This allows selection of preempting and non preempting interrupt levels. Support for tail-chaining, and late arrival, of interrupts. This enables back-to-back interrupt processing without the overhead of state saving and restoration ...
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Flash Program Memory Flash memory in PSoC devices provides nonvolatile storage for user firmware, user configuration data, bulk data storage, and optional ECC data. The main flash memory area contains up to 256 KB of user program space. Up ...
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Data, Address, and Control Signals PHUB Data, Address, and Control Signals Data, Address, and Control Signals 5.6 Memory Map The Cortex-M3 has a fixed address map, which allows peripherals to be accessed by simple memory access instructions. 5.6.1 Address Map ...
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Table 5-3. Peripheral Data Address Map Address Range 0x00000000 – 0x0003FFFF 256 K Flash 0x1FFF8000 – 0x1FFFFFFF 32 K SRAM in Code region 0x20000000 – 0x20007FFF 32 K SRAM in SRAM region 0x40004000 – 0x400042FF Clocking, PLLs, and oscillators 0x40004300 ...
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Table 6-1. Oscillator Summary Source Fmin Tolerance at Fmin IMO 3 MHz ±1% over voltage and temperature MHzECO 4 MHz Crystal dependent DSI 0 MHz Input dependent PLL 24 MHz Input dependent Doubler 12 MHz Input dependent ILO 1 kHz ...
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The PLL outputs clock frequencies in the range MHz. Its input and feedback dividers supply 4032 discrete ratios to create almost any desired ...
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Clock Distribution All seven clock sources are inputs to the central clock distribution system. The distribution system is designed to create multiple high precision clocks. These clocks are customized for the design’s requirements and eliminate the common problems found ...
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Power Modes PSoC 5 devices have four different power modes, as shown in Table 6-2 and Table 6-3. The power modes allow a design to easily provide required functionality and processing power while simultaneously minimizing power consumption and maximizing ...
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Figure 6-5. Power Mode Transitions Active Manual Sleep Buzz Alternate Active 6.2.1.1 Active Mode Active mode is the primary operating mode of the device. When in active mode, the active configuration template bits control which available resources are enabled or ...
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The external 32 kHz crystal can be used to generate inductor boost pulses on the rising and falling edge of the clock when the output voltage is less than the programmed value. This is called ...
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At these times the PRES circuit is also buzzed to allow periodic voltage monitoring. ALVI, DLVI, AHVI - Analog/Digital Low Voltage Interrupt, Analog High Voltage Interrupt Interrupt circuits are available to detect when ...
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No analog input or LCD capability Over voltage tolerance up to 5.5 V SIO can act as a general purpose analog comparator USBIO features: Full speed USB 2.0 compliant I/O Highest drive strength for general ...
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Digital Input Path PRT[x]SIO_HYST_EN PRT[x]SIO_DIFF Reference Level PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Pin Interrupt Signal PICU[x]INTSTAT Digital Output Path Reference Level PRT[x]SIO_CFG PRT[x]SLW PRT[x]SYNC_OUT PRT[x]DR Digital System Output PRT[x]BYP PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Digital Input Path ...
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Drive Modes Each GPIO and SIO pin is individually configurable into one of the eight drive modes listed in Table 6-6. Three configuration bits are used for each pin (DM[2:0]) and set in the PRTxDM[2:0] registers. Figure 6-11 depicts ...
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Resistive Pull Up or Resistive Pull Down Resistive pull up or pull down, respectively, provides a series resistance in one of the data states and strong drive in the other. Pins can be used for digital input and output ...
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Adjustable Output Level This section applies only to SIO pins. SIO port pins support the ability to provide a regulated high output level for interface to external signals that are lower in voltage than the SIO’s respective V . ...
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Digital Subsystem The digital programmable system creates application specific combinations of both standard and advanced digital peripherals and custom logic functions. These peripherals and logic are then interconnected to each other and to any pin on the device, providing ...
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Designing with PSoC Creator 7.1.4.1 More Than a Typical IDE A successful design tool allows for the rapid development and deployment of both simple and complex designs. It reduces or eliminates any learning curve. It makes the integration of ...
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Component Catalog Figure 7-3. Component Catalog The component catalog is a repository of reusable design elements that select device functionality and customize your PSoC device populated with an impressive selection of content; from simple primitives such as ...
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PSoC Creator contains all the tools necessary to complete a design, and then to maintain and extend that design for years to come. All steps of the design flow are carefully integrated and optimized for ease-of-use and to maximize productivity. ...
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Input Muxes Input from Programmable Routing 6 PI Parallel Input/Output (To/From Programmable Routing) PO 7.2.2.6 Working Registers The datapath contains six primary working registers, which are accessed by CPU firmware or DMA during normal operation. Table 7-1. Working Datapath Registers ...
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Conditionals Each datapath has two compares, with bit masking options. Compare operands include the two accumulators and the two data registers in a variety of configurations. Other conditions include zero detect, all ones detect, and overflow. These conditions are ...
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Other interfaces that are not explicitly shown include the system interfaces for bus and clock distribution. The UDB array includes multiple horizontal and vertical routing channels each comprised of 96 wires. The wire connections to UDBs, ...
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Figure 7-13. Digital System Interconnect Timer Interrupt DMA CAN I2C Counters Controller Controller Digital System Routing I/F UDB ARRAY Digital System Routing I/F Global SAR EMIF DAC Comparators Clocks ADC Interrupt and DMA routing is very flexible in the CY8C52 ...
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ISO-11898-1 standard. The CAN protocol was originally designed for automotive applications with a focus on a high level of fault detection. This ensures high communication reliability at a low cost. Because of its success in automotive applications, ...
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Tx Buffer Status TxReq Pending TxInterrupt Request (if enabled) RxMessage0 Acceptance Code 0 Rx Buffer Status RxMessage RxMessage1 Acceptance Code 1 Available RxMessage14 Acceptance Code 14 RxInterrupt RxMessage15 Acceptance Code 15 Request (if enabled) 7.6 USB PSoC includes a dedicated ...
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Timers, Counters, and PWMs The Timer/Counter/PWM peripheral is a 16-bit dedicated peripheral providing three of the most common embedded peripheral features. As almost all embedded systems use some combination of timers, counters, and PWMs. Four of them have been ...
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GPIO Port DSI Array The PSoC Creator software program provides a user-friendly interface to configure the analog connections between the GPIO and various analog resources and also ...
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ExVrefL ExVrefL1 GPIO P0[4] GPIO P0[5] GPIO * i0 P0[6] GPIO * P0[7] cmp0_vref (1.024V) GPIO cmp_muxvn[1:0] P4[2] vref_cmp1 cmp1_vref (0.256V) bg_vda_res_en GPIO Vdda Vdda/2 P4[3] refbuf_vref1 (1.024V) GPIO refbuf_vref2 (1.2V) P4[4] refsel[1:0] GPIO vssa P4[5] ...
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Analog local buses (abus) are routing resources located within the analog subsystem and are used to route signals between different analog blocks. There are eight abus routes in CY8C38, four in the left half (abusl [0:3]) and four in the ...
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From Analog Routing 8.3.2 LUT The CY8C52 family of devices contains two LUTs. The LUT is a two input, one output lookup table that is driven by one or two of the comparators in the chip. The output of any ...
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Ability to invert LCD display for negative image Three LCD driver drive modes, allowing power optimization LCD driver configurable to be active when PSoC is in limited active mode Figure 8-5. LCD System LCD Global DAC Clock ...
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Current DAC The IDAC can be configured for the ranges µ 256 µA, and 0 to 2.048 mA. The IDAC can be configured to source or sink current. 8.7.2 Voltage DAC For the VDAC, ...
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Standard JTAG programming and debugging interfaces make CY8C52 compatible with other popular third-party tools (for example, ARM / Keil) 9.4 Trace Features The following trace features are supported: Instruction trace Data watchpoint on access to data address, address ...
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Development Support The CY8C52 family has a rich set of documentation, development tools, and online resources to assist you during your development process. Visit psoc.cypress.com/getting-started to find out more. 10.1 Documentation A suite of documentation, to ensure that you ...
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Electrical Specifications Specifications are valid for –40 °C T 85 °C and T A except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator components, ...
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Device Level Specifications Specifications are valid for –40 °C T 85 °C and T A except where noted. 11.2.1 Device Level Specifications Table 11-2. DC Specifications Parameter Description V Analog supply voltage and input to DDA analog ...
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Table 11-2. DC Specifications (continued) Parameter Description I2C Wake = ON CPU = OFF RTC = OFF Sleep timer = OFF WDT = OFF Comparator = OFF POR = ON Boost = OFF SIO pins in single ended input, unregulated ...
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Power Regulators Specifications are valid for –40 °C T 85 °C and T A except where noted. 11.3.1 Digital Core Regulator Table 11-4. Digital Core Regulator DC Specifications Parameter Description V Input voltage DDD V Output voltage ...
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Table 11-6. Inductive Boost Regulator DC Specifications (continued) Parameter Description [23] Boost output voltage range 1.8 V 1.9 V 2 BOOST 2.7 V 3.0 V 3.3 V 3.6 V 5.0 V Load regulation Line regulation Efficiency ...
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Inputs and Outputs Specifications are valid for –40 °C T 85 °C and T A except where noted. 11.4.1 GPIO Table 11-8. GPIO DC Specifications Parameter Description V Input voltage high threshold IH V Input voltage low ...
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SIO Table 11-10. SIO DC Specifications Parameter Description Vinref Input voltage reference (Differential input mode) Output voltage reference (Regulated output mode) Voutref Input voltage high threshold V GPIO mode IH Differential input mode Input voltage low threshold V GPIO ...
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Table 11-11. SIO AC Specifications (continued) Parameter Description SIO output operating frequency 3.3 V < V < 5.5 V, Unregulated DDIO output (GPIO) mode, fast strong drive mode 1.71 V < V < 3.3 V, Unregu- DDIO lated output (GPIO) ...
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Table 11-13. USBIO AC Specifications Parameter Description Tdrate Full-speed data rate average bit rate Tjr1 Receiver data jitter tolerance to next transition Tjr2 Receiver data jitter tolerance to pair transition Tdj1 Driver differential jitter to next transition Tdj2 Driver differential ...
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Analog Peripherals Specifications are valid for –40 °C T 85 °C and T A except where noted. 11.5.1 Voltage Reference Table 11-17. Voltage Reference Specifications Parameter Description V Precision reference voltage REF [27] Temperature drift Long term ...
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Analog Globals Table 11-20. Analog Globals AC Specifications Parameter Description Rppag Resistance pin-to-pin through [28] analog global Rppmuxbus Resistance pin-to-pin through [28] analog mux bus BWag 3 dB bandwidth of analog globals CMRRag Common mode rejection for differential signals ...
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VDAC Table 11-23. VDAC (Voltage Digital-to-Analog Converter) DC Specifications Parameter Description Resolution [30] Output resistance R High OUT Low [30] Output voltage range V High OUT Low INL Integral non linearity DNL Differential non linearity Ezs Zero scale error ...
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LCD Direct Drive Table 11-26. LCD Direct Drive DC Specifications Parameter Description I LCD operating current CC V LCD bias range (V refers to the BIAS BIAS main output voltage(V0) of LCD DAC) LCD bias step size LCD capacitance ...
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Digital Peripherals Specifications are valid for –40 °C T 85 °C and T A except where noted. 11.6.1 Timer Table 11-28. Timer DC Specifications Parameter Description Block current consumption 3 MHz 12 MHz 40 MHz Table 11-29. ...
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Pulse Width Modulation Table 11-32. PWM DC Specifications Parameter Description Block current consumption 3 MHz 12 MHz 40 MHz Table 11-33. PWM AC Specifications Parameter Description Operating frequency Pulse width Pulse width (external) Kill pulse width Kill pulse width ...
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USB Table 11-38. USB DC Specifications Parameter Description Operating current 11.6.7 Universal Digital Blocks (UDBs) PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so ...
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Memory Specifications are valid for –40 °C T 85 °C and T A except where noted. 11.7.1 Flash Table 11-40. Flash DC Specifications Parameter Description Erase and program voltage Table 11-41. Flash AC Specifications Parameter Description T ...
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Table 11-45. NVL AC Specifications Parameter Description NVL endurance NVL data retention time 11.7.4 SRAM Table 11-46. SRAM DC Specifications Parameter Description V SRAM retention voltage SRAM Table 11-47. SRAM AC Specifications Parameter Description F SRAM operating frequency SRAM 11.7.5 ...
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Table 11-48. Asynchronous Read Cycle Specifications (continued) Parameter Description Toel EM_OEn low time Toeh EM_OEn high to EM_CEn high hold time Tdoesu Data to EM_OEn high setup time Tdcesu Data to EM_CEn high setup time Tdoeh Data hold time after ...
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Tcp EM_ Clock Tceld EM_ CEn Taddrv EM_ Addr Toeld EM_ OEn EM_ Data Tadscld EM_ ADSCn Table 11-50. Synchronous Read Cycle Specifications Parameter Description T EMIF clock period Tcp EM_clock period Tceld EM_clock low to EM_CEn low Tcehd EM_clock ...
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Tcp EM_ Clock Tceld EM_ CEn Taddrv EM_ Addr Tweld EM_ WEn Tds EM_ Data Tadscld EM_ ADSCn Table 11-51. Synchronous Write Cycle Specifications Parameter Description T EMIF clock period Tcp EM_clock period Tceld EM_clock low to EM_CEn low Tcehd ...
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PSoC System Resources Specifications are valid for –40 °C T 85 °C and T A except where noted. 11.8.1 POR with Brown Out For brown out detect in regulated mode, V Table 11-52. Precise Power On Reset ...
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Interrupt Controller Table 11-56. Interrupt Controller AC Specifications Parameter Description Delay from interrupt signal input to ISR code execution from main line code Delay from interrupt signal input to ISR code execution from ISR code 11.8.4 JTAG Interface Table ...
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Clocking Specifications are valid for –40 °C T 85 °C and T A except where noted. 11.9.1 32 kHz External Crystal Table 11-60. 32 kHz External Crystal DC Specifications Parameter Description I Operating current CC CL External ...
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Internal Low Speed Oscillator Table 11-64. ILO DC Specifications Parameter Description Operating current I CC Leakage current Table 11-65. ILO AC Specifications Parameter Description Startup time Startup time Startup time Duty cycle ILO frequencies (trimmed) 100 kHz 1 kHz ...
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Phase-Locked Loop Table 11-68. PLL DC Specifications Parameter Description I PLL operating current DD Table 11-69. PLL AC Specifications Parameter Description [40] Fpllin PLL input frequency PLL intermediate frequency [40] Fpllout PLL output frequency Lock time at startup [42] ...
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... Table 12-1. CY8C52 Family with ARM Cortex-M3 CPU MCU Core Part Number 32 KB Flash ✔ 1x12-bit SAR 1 CY8C5245PVI-112 ✔ 1x12-bit SAR 1 CY8C5245PVI-113 Flash ✔ 1x12-bit SAR 1 CY8C5246AXI-038 CY8C5246LTI-087 ✔ 1x12-bit SAR 1 CY8C5246PVI-071 ✔ 1x12-bit SAR 1 ✔ 1x12-bit SAR 1 CY8C5246AXI-054 ✔ 1x12-bit SAR 1 ...
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Table 12-1. CY8C52 Family with ARM Cortex-M3 CPU ✔ 1x12-bit SAR 1 CY8C5248AXI-047 40 256 64 2 ✔ 1x12-bit SAR 1 CY8C5248LTI-030 40 256 64 2 CY8C5248PVI-024 40 256 64 2 ✔ 1x12-bit SAR 1 CY8C5248AXI-078 40 256 64 2 ...
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A high level review of the Cypress Pb-free position is available on our website. Specific package information is also available. Package Material Declaration Datasheets (PMDDs) identify all substances contained within Cypress packages. PMDDs also confirm the absence of many banned ...
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Figure 13-2. 68-pin QFN 8x8 with 0.4 mm Pitch Package Outline (Sawn Version) TOP VIEW 8.000±0.100 PIN 1 DOT LASER MARK NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED METAL. 2. REFERENCE JEDEC#: MO-220 ...
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Acronyms Table 14-1. Acronyms Used in this Document Acronym Description abus analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced microcontroller bus archi- tecture) high-performance bus, an ARM data transfer bus ALU arithmetic logic unit AMUXBUS ...
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Table 14-1. Acronyms Used in this Document (continued) Acronym Description PHUB peripheral hub PHY physical layer PICU port interrupt control unit PLA programmable logic array PLD programmable logic device, see also PAL PLL phase-locked loop PMDD package material declaration datasheet ...
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Document Conventions 16.1 Units of Measure Table 16-1. Units of Measure Symbol Unit of Measure °C degrees Celsius dB decibels fF femtofarads Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohours kHz kilohertz k kilohms ksps kilosamples ...
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Revision History ® Description Title: PSoC 5: CY8C52 Family Datasheet Programmable System-on-Chip (PSoC Document Number: 001-55034 Submission Rev. ECN No. Date ** 2759055 09/02/09 *A 2824626 12/09/09 *B 2873520 02/04/10 Document Number: 001-55034 Rev. *G PRELIMINARY ® PSoC 5: ...
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Description Title: PSoC 5: CY8C52 Family Datasheet Programmable System-on-Chip (PSoC Document Number: 001-55034 *C 2911720 04/13/10 Document Number: 001-55034 Rev. *G PRELIMINARY ® PSoC 5: CY8C52 Family Datasheet MKEA Updated Vb pin in PCB Schematic. Updated Tstartup parameter in ...
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Description Title: PSoC 5: CY8C52 Family Datasheet Programmable System-on-Chip (PSoC Document Number: 001-55034 *D 2936486 05/24/10 *E 2944841 6/4/2010 *F 2960407 06/24/10 *G 3019464 08/31/10 Document Number: 001-55034 Rev. *G PRELIMINARY ® PSoC 5: CY8C52 Family Datasheet MKEA Replaced ...
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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...