CY7C63231A-PC Cypress Semiconductor Corp, CY7C63231A-PC Datasheet - Page 26

• Manufacturer Part Number: CY7C63231A-PC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C63231A-PC

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Not Compliant

Bit 6: IN Received
Bit 5: OUT Received
Bit 4: ACKed Transaction
Bit [3:0]: Mode Bit[3:0]
14.3
The feature one non-control endpoint, endpoint 1 (EP1). The EP1 Mode Register does not have the locking mechanism of the
EP0 Mode Register. The EP1 Mode Register uses the format shown in Figure 14-3. EP1 uses an 8-byte FIFO at SRAM locations
0xF0–0xF7 as shown in Section 8.2.
Bit 7: STALL
Bit [6:5]: Reserved. Must be written to zero during register writes.
Bit 4: ACKed Transaction
Document #: 38-08028 Rev. *B
Read/Write
Bit Name
While this bit is set to ‘1’, the CPU cannot write to the EP0 FIFO. This prevents firmware from overwriting an incoming SETUP
transaction before firmware has a chance to read the SETUP data.
0 = No SETUP received. This bit is cleared by any non-locked writes to the register.
1 = A valid IN packet has been received. This bit is updated to ‘1’ after the last received packet in an IN transaction. This bit
is cleared by any non-locked writes to the register.
0 = No IN received. This bit is cleared by any non-locked writes to the register.
1 = A valid OUT packet has been received. This bit is updated to ‘1’ after the last received packet in an OUT transaction. This
bit is cleared by any non-locked writes to the register.
0 = No OUT received. This bit is cleared by any non-locked writes to the register.
The ACKed Transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an
ACK packet.
1 = The transaction completes with an ACK
0 = The transaction does not complete with an ACK
The endpoint modes determine how the SIE responds to USB traffic that the host sends to the endpoint. For example, if the
endpoint Mode Bits [3:0] are set to 0001 which is NAK IN/OUT mode as shown in Table 20-1, the SIE will send NAK hand-
shakes in response to any IN or OUT token sent to this endpoint. In this NAK IN/OUT mode, the SIE will send an ACK
handshake when the host sends a SETUP token to this endpoint. The mode encoding is shown in Table 20-1. Additional
information on the mode bits can be found in Table 20-2 and Table 20-3. These modes give the firmware total control on how
to respond to different tokens sent to the endpoints from the host.
In addition, the Mode Bits are automatically changed by the SIE in response to many USB transactions. For example, if the
Mode Bit [3:0] are set to 1011 which is ACK OUT-NAK IN mode as shown in Table 20-1, the SIE will change the endpoint Mode
Bit [3:0] to NAK IN/OUT (0001) mode after issuing an ACK handshake in response to an OUT token. Firmware needs to update
the mode for the SIE to respond appropriately.
1 = The SIE will stall an OUT packet if the Mode Bits are set to ACK-OUT, and the SIE will stall an IN packet if the mode bits
are set to ACK-IN. See Section 20.0 for the available modes.
0 = This bit must be set to LOW for all other modes.
The ACKed transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an
ACK packet.
1 = The transaction completes with an ACK.
0 = The transaction does not complete with an ACK.
Reset
Bit #
USB Non-Control Endpoints
STALL
R/W
7
0
Figure 14-3. USB Endpoint EP1 Mode Registers (Address 0x14)
6
0
-
Reserved
FOR
FOR
5
0
-
Transaction
ACKed
R/C
4
0
R/W
3
0
R/W
2
0
CY7C63221/31A
Mode Bit
enCoRe™ USB
R/W
1
0
Page 26 of 50
R/W
0
0
[+] Feedback