ISP1581BD STEricsson, ISP1581BD Datasheet - Page 31

• Manufacturer Part Number: ISP1581BD
• Manufacturer: STEricsson

Specifications of ISP1581BD

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
Table 28:
9397 750 13462
Product data
Bit
Symbol
Reset
Bus reset
Access
DMA Command register: bit allocation
9.4.1 DMA Command register (address: 30H)
7
Table 27:
Remark: The DMA bus defaults to three-state, until a DMA command is executed. All
the other control signals are not three-stated.
The DMA Command register is a 1-byte register that initiates all DMA transfer activity
on the DMA Controller. The register is write-only: reading it will return FFH.
Remark: The DMA bus will be in three-state until a DMA command is executed.
Table 29:
Control bits
DMA Hardware register (see
MASTER
MDMA read/write (opcode = 06H/07H)
DMA Configuration register (see
DMA_MODE[1:0]
ATA_MODE
DMA Hardware register (see
MASTER
UDMA read/write (opcode = 02H/03H)
DMA Configuration register (see
DMA_MODE[1:0]
IGNORE_IORDY
ATA_MODE
DMA Hardware register (see
MASTER
Bit
7:0
6
Control bits for IDE-specified DMA transfers
DMA Command register: bit description
Symbol
DMA_CMD[7:0]
Rev. 06 — 23 December 2004
5
Table 35
Table 35
Table 35
Description
DMA command code, see
DMA_CMD[7:0]
4
Table 33
Table 33
Description
set to logic 0
selects the MDMA mode; timings are ATA(PI) compatible
set to logic 1 (ATA transfer)
set to logic 0
selects the UDMA mode; timings are ATA(PI) compatible
used to ignore the IORDY pin during transfer
set to logic 1 (ATA transfer)
set to logic 0
FFH
FFH
and
and
and
W
and
and
Table
Table
Table
3
Table
Table
36)
36)
36)
Hi-Speed USB peripheral controller
34)
34)
Table
…continued
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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