ISP1583BSGA STEricsson, ISP1583BSGA Datasheet - Page 94

• Manufacturer Part Number: ISP1583BSGA
• Manufacturer: STEricsson

Specifications of ISP1583BSGA

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

21. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. POR timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Fig 11. Clock with respect to the external POR . . . . . . . .22
Fig 12. ISP1583 with a 3.3 V supply . . . . . . . . . . . . . . . .23
Fig 13. Power-sharing mode . . . . . . . . . . . . . . . . . . . . . .24
Fig 14. Interrupt pin status during power off in
Fig 15. Self-powered mode . . . . . . . . . . . . . . . . . . . . . . .26
Fig 16. Bus-powered mode . . . . . . . . . . . . . . . . . . . . . . .27
Fig 17. Programmable strobe timing . . . . . . . . . . . . . . . .59
Fig 18. Source differential data-to-EOP transition skew and
Fig 19. Receiver differential data jitter . . . . . . . . . . . . . . .69
Fig 20. Receiver SE0 width tolerance . . . . . . . . . . . . . . .69
Fig 21. ISP1583 register access timing: separate address
Fig 22. ISP1583 ready signal timing . . . . . . . . . . . . . . . .71
Fig 23. ISP1583 register access timing: separate address
Fig 24. ISP1583 ready signal timing . . . . . . . . . . . . . . . .72
Fig 25. EOT timing in generic processor mode . . . . . . . .73
Fig 26. ISP1583 register access timing: multiplexed
Fig 27. ISP1583 register access timing: multiplexed
Fig 28. ISP1583 register access timing: multiplexed
Fig 29. ISP1583 register access timing: multiplexed
Fig 30. EOT timing in split bus mode . . . . . . . . . . . . . . . .78
Fig 31. PIO mode timing . . . . . . . . . . . . . . . . . . . . . . . . .80
Fig 32. GDMA slave mode timing: DIOR (master) and
Fig 33. GDMA slave mode timing: DIOR (master) or DACK
Fig 34. GDMA slave mode timing: DACK (master and
Fig 35. MDMA master mode timing . . . . . . . . . . . . . . . . .83
Fig 36. Typical interface connections for generic processor
Fig 37. Typical interface connections for split bus mode
Fig 38. Load impedance for the DP and DM pins (full-speed
ISP1583_11
Product data sheet
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pin configuration ISP1583BS (top view) . . . . . . . .5
Pin configuration ISP1583ET and ISP1583ET2 (top
view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin configuration ISP1583ET1 (top view) . . . . . . .6
Interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Behavior of bit GLINTENA . . . . . . . . . . . . . . . . . .20
Resistor and electrolytic or tantalum capacitor
needed for V
Oscilloscope reading: no resistor and capacitor in
the network . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Oscilloscope reading: with resistor and capacitor in
the network . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
power-sharing mode . . . . . . . . . . . . . . . . . . . . . .24
EOP width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
and data buses (8051 mode) . . . . . . . . . . . . . . . .70
and data buses (Freescale mode) . . . . . . . . . . . .72
address/data bus (8051 mode) . . . . . . . . . . . . . .74
address/data bus (Freescale mode) . . . . . . . . . .75
address/data bus (A0 function and 8051 mode) .76
address/data bus (A0 function and Freescale
mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
DIOW (slave) . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
(slave) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
slave) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
(slave mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
BUS
sensing . . . . . . . . . . . . . . . . . . .21
Rev. 11 — 20 November 2009
Fig 39. Package outline SOT804-1 (HVQFN64) . . . . . . . 86
Fig 40. Package outline SOT543-1 (TFBGA64) . . . . . . . 87
Fig 41. Package outline SOT969-1 (TFBGA64) . . . . . . . 88
mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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